1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) ST-Ericsson SA 2012
4 *
5 * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
6 * for ST-Ericsson.
7 */
8
9
10 #ifndef UX500_MSP_I2S_H
11 #define UX500_MSP_I2S_H
12
13 #include <linux/platform_device.h>
14
15 #define MSP_INPUT_FREQ_APB 48000000
16
17 /*** Stereo mode. Used for APB data accesses as 16 bits accesses (mono),
18 * 32 bits accesses (stereo).
19 ***/
20 enum msp_stereo_mode {
21 MSP_MONO,
22 MSP_STEREO
23 };
24
25 /* Direction (Transmit/Receive mode) */
26 enum msp_direction {
27 MSP_TX = 1,
28 MSP_RX = 2
29 };
30
31 /* Transmit and receive configuration register */
32 #define MSP_BIG_ENDIAN 0x00000000
33 #define MSP_LITTLE_ENDIAN 0x00001000
34 #define MSP_UNEXPECTED_FS_ABORT 0x00000000
35 #define MSP_UNEXPECTED_FS_IGNORE 0x00008000
36 #define MSP_NON_MODE_BIT_MASK 0x00009000
37
38 /* Global configuration register */
39 #define RX_ENABLE 0x00000001
40 #define RX_FIFO_ENABLE 0x00000002
41 #define RX_SYNC_SRG 0x00000010
42 #define RX_CLK_POL_RISING 0x00000020
43 #define RX_CLK_SEL_SRG 0x00000040
44 #define TX_ENABLE 0x00000100
45 #define TX_FIFO_ENABLE 0x00000200
46 #define TX_SYNC_SRG_PROG 0x00001800
47 #define TX_SYNC_SRG_AUTO 0x00001000
48 #define TX_CLK_POL_RISING 0x00002000
49 #define TX_CLK_SEL_SRG 0x00004000
50 #define TX_EXTRA_DELAY_ENABLE 0x00008000
51 #define SRG_ENABLE 0x00010000
52 #define FRAME_GEN_ENABLE 0x00100000
53 #define SRG_CLK_SEL_APB 0x00000000
54 #define RX_FIFO_SYNC_HI 0x00000000
55 #define TX_FIFO_SYNC_HI 0x00000000
56 #define SPI_CLK_MODE_NORMAL 0x00000000
57
58 #define MSP_FRAME_SIZE_AUTO -1
59
60 #define MSP_DR 0x00
61 #define MSP_GCR 0x04
62 #define MSP_TCF 0x08
63 #define MSP_RCF 0x0c
64 #define MSP_SRG 0x10
65 #define MSP_FLR 0x14
66 #define MSP_DMACR 0x18
67
68 #define MSP_IMSC 0x20
69 #define MSP_RIS 0x24
70 #define MSP_MIS 0x28
71 #define MSP_ICR 0x2c
72 #define MSP_MCR 0x30
73 #define MSP_RCV 0x34
74 #define MSP_RCM 0x38
75
76 #define MSP_TCE0 0x40
77 #define MSP_TCE1 0x44
78 #define MSP_TCE2 0x48
79 #define MSP_TCE3 0x4c
80
81 #define MSP_RCE0 0x60
82 #define MSP_RCE1 0x64
83 #define MSP_RCE2 0x68
84 #define MSP_RCE3 0x6c
85 #define MSP_IODLY 0x70
86
87 #define MSP_ITCR 0x80
88 #define MSP_ITIP 0x84
89 #define MSP_ITOP 0x88
90 #define MSP_TSTDR 0x8c
91
92 #define MSP_PID0 0xfe0
93 #define MSP_PID1 0xfe4
94 #define MSP_PID2 0xfe8
95 #define MSP_PID3 0xfec
96
97 #define MSP_CID0 0xff0
98 #define MSP_CID1 0xff4
99 #define MSP_CID2 0xff8
100 #define MSP_CID3 0xffc
101
102 /* Protocol dependant parameters list */
103 #define RX_ENABLE_MASK BIT(0)
104 #define RX_FIFO_ENABLE_MASK BIT(1)
105 #define RX_FSYNC_MASK BIT(2)
106 #define DIRECT_COMPANDING_MASK BIT(3)
107 #define RX_SYNC_SEL_MASK BIT(4)
108 #define RX_CLK_POL_MASK BIT(5)
109 #define RX_CLK_SEL_MASK BIT(6)
110 #define LOOPBACK_MASK BIT(7)
111 #define TX_ENABLE_MASK BIT(8)
112 #define TX_FIFO_ENABLE_MASK BIT(9)
113 #define TX_FSYNC_MASK BIT(10)
114 #define TX_MSP_TDR_TSR BIT(11)
115 #define TX_SYNC_SEL_MASK (BIT(12) | BIT(11))
116 #define TX_CLK_POL_MASK BIT(13)
117 #define TX_CLK_SEL_MASK BIT(14)
118 #define TX_EXTRA_DELAY_MASK BIT(15)
119 #define SRG_ENABLE_MASK BIT(16)
120 #define SRG_CLK_POL_MASK BIT(17)
121 #define SRG_CLK_SEL_MASK (BIT(19) | BIT(18))
122 #define FRAME_GEN_EN_MASK BIT(20)
123 #define SPI_CLK_MODE_MASK (BIT(22) | BIT(21))
124 #define SPI_BURST_MODE_MASK BIT(23)
125
126 #define RXEN_SHIFT 0
127 #define RFFEN_SHIFT 1
128 #define RFSPOL_SHIFT 2
129 #define DCM_SHIFT 3
130 #define RFSSEL_SHIFT 4
131 #define RCKPOL_SHIFT 5
132 #define RCKSEL_SHIFT 6
133 #define LBM_SHIFT 7
134 #define TXEN_SHIFT 8
135 #define TFFEN_SHIFT 9
136 #define TFSPOL_SHIFT 10
137 #define TFSSEL_SHIFT 11
138 #define TCKPOL_SHIFT 13
139 #define TCKSEL_SHIFT 14
140 #define TXDDL_SHIFT 15
141 #define SGEN_SHIFT 16
142 #define SCKPOL_SHIFT 17
143 #define SCKSEL_SHIFT 18
144 #define FGEN_SHIFT 20
145 #define SPICKM_SHIFT 21
146 #define TBSWAP_SHIFT 28
147
148 #define RCKPOL_MASK BIT(0)
149 #define TCKPOL_MASK BIT(0)
150 #define SPICKM_MASK (BIT(1) | BIT(0))
151 #define MSP_RX_CLKPOL_BIT(n) ((n & RCKPOL_MASK) << RCKPOL_SHIFT)
152 #define MSP_TX_CLKPOL_BIT(n) ((n & TCKPOL_MASK) << TCKPOL_SHIFT)
153
154 #define P1ELEN_SHIFT 0
155 #define P1FLEN_SHIFT 3
156 #define DTYP_SHIFT 10
157 #define ENDN_SHIFT 12
158 #define DDLY_SHIFT 13
159 #define FSIG_SHIFT 15
160 #define P2ELEN_SHIFT 16
161 #define P2FLEN_SHIFT 19
162 #define P2SM_SHIFT 26
163 #define P2EN_SHIFT 27
164 #define FSYNC_SHIFT 15
165
166 #define P1ELEN_MASK 0x00000007
167 #define P2ELEN_MASK 0x00070000
168 #define P1FLEN_MASK 0x00000378
169 #define P2FLEN_MASK 0x03780000
170 #define DDLY_MASK 0x00003000
171 #define DTYP_MASK 0x00000600
172 #define P2SM_MASK 0x04000000
173 #define P2EN_MASK 0x08000000
174 #define ENDN_MASK 0x00001000
175 #define TFSPOL_MASK 0x00000400
176 #define TBSWAP_MASK 0x30000000
177 #define COMPANDING_MODE_MASK 0x00000c00
178 #define FSYNC_MASK 0x00008000
179
180 #define MSP_P1_ELEM_LEN_BITS(n) (n & P1ELEN_MASK)
181 #define MSP_P2_ELEM_LEN_BITS(n) (((n) << P2ELEN_SHIFT) & P2ELEN_MASK)
182 #define MSP_P1_FRAME_LEN_BITS(n) (((n) << P1FLEN_SHIFT) & P1FLEN_MASK)
183 #define MSP_P2_FRAME_LEN_BITS(n) (((n) << P2FLEN_SHIFT) & P2FLEN_MASK)
184 #define MSP_DATA_DELAY_BITS(n) (((n) << DDLY_SHIFT) & DDLY_MASK)
185 #define MSP_DATA_TYPE_BITS(n) (((n) << DTYP_SHIFT) & DTYP_MASK)
186 #define MSP_P2_START_MODE_BIT(n) ((n << P2SM_SHIFT) & P2SM_MASK)
187 #define MSP_P2_ENABLE_BIT(n) ((n << P2EN_SHIFT) & P2EN_MASK)
188 #define MSP_SET_ENDIANNES_BIT(n) ((n << ENDN_SHIFT) & ENDN_MASK)
189 #define MSP_FSYNC_POL(n) ((n << TFSPOL_SHIFT) & TFSPOL_MASK)
190 #define MSP_DATA_WORD_SWAP(n) ((n << TBSWAP_SHIFT) & TBSWAP_MASK)
191 #define MSP_SET_COMPANDING_MODE(n) ((n << DTYP_SHIFT) & \
192 COMPANDING_MODE_MASK)
193 #define MSP_SET_FSYNC_IGNORE(n) ((n << FSYNC_SHIFT) & FSYNC_MASK)
194
195 /* Flag register */
196 #define RX_BUSY BIT(0)
197 #define RX_FIFO_EMPTY BIT(1)
198 #define RX_FIFO_FULL BIT(2)
199 #define TX_BUSY BIT(3)
200 #define TX_FIFO_EMPTY BIT(4)
201 #define TX_FIFO_FULL BIT(5)
202
203 #define RBUSY_SHIFT 0
204 #define RFE_SHIFT 1
205 #define RFU_SHIFT 2
206 #define TBUSY_SHIFT 3
207 #define TFE_SHIFT 4
208 #define TFU_SHIFT 5
209
210 /* Multichannel control register */
211 #define RMCEN_SHIFT 0
212 #define RMCSF_SHIFT 1
213 #define RCMPM_SHIFT 3
214 #define TMCEN_SHIFT 5
215 #define TNCSF_SHIFT 6
216
217 /* Sample rate generator register */
218 #define SCKDIV_SHIFT 0
219 #define FRWID_SHIFT 10
220 #define FRPER_SHIFT 16
221
222 #define SCK_DIV_MASK 0x0000003FF
223 #define FRAME_WIDTH_BITS(n) (((n) << FRWID_SHIFT) & 0x0000FC00)
224 #define FRAME_PERIOD_BITS(n) (((n) << FRPER_SHIFT) & 0x1FFF0000)
225
226 /* DMA controller register */
227 #define RX_DMA_ENABLE BIT(0)
228 #define TX_DMA_ENABLE BIT(1)
229
230 #define RDMAE_SHIFT 0
231 #define TDMAE_SHIFT 1
232
233 /* Interrupt Register */
234 #define RX_SERVICE_INT BIT(0)
235 #define RX_OVERRUN_ERROR_INT BIT(1)
236 #define RX_FSYNC_ERR_INT BIT(2)
237 #define RX_FSYNC_INT BIT(3)
238 #define TX_SERVICE_INT BIT(4)
239 #define TX_UNDERRUN_ERR_INT BIT(5)
240 #define TX_FSYNC_ERR_INT BIT(6)
241 #define TX_FSYNC_INT BIT(7)
242 #define ALL_INT 0x000000ff
243
244 /* MSP test control register */
245 #define MSP_ITCR_ITEN BIT(0)
246 #define MSP_ITCR_TESTFIFO BIT(1)
247
248 #define RMCEN_BIT 0
249 #define RMCSF_BIT 1
250 #define RCMPM_BIT 3
251 #define TMCEN_BIT 5
252 #define TNCSF_BIT 6
253
254 /* Single or dual phase mode */
255 enum msp_phase_mode {
256 MSP_SINGLE_PHASE,
257 MSP_DUAL_PHASE
258 };
259
260 /* Frame length */
261 enum msp_frame_length {
262 MSP_FRAME_LEN_1 = 0,
263 MSP_FRAME_LEN_2 = 1,
264 MSP_FRAME_LEN_4 = 3,
265 MSP_FRAME_LEN_8 = 7,
266 MSP_FRAME_LEN_12 = 11,
267 MSP_FRAME_LEN_16 = 15,
268 MSP_FRAME_LEN_20 = 19,
269 MSP_FRAME_LEN_32 = 31,
270 MSP_FRAME_LEN_48 = 47,
271 MSP_FRAME_LEN_64 = 63
272 };
273
274 /* Element length */
275 enum msp_elem_length {
276 MSP_ELEM_LEN_8 = 0,
277 MSP_ELEM_LEN_10 = 1,
278 MSP_ELEM_LEN_12 = 2,
279 MSP_ELEM_LEN_14 = 3,
280 MSP_ELEM_LEN_16 = 4,
281 MSP_ELEM_LEN_20 = 5,
282 MSP_ELEM_LEN_24 = 6,
283 MSP_ELEM_LEN_32 = 7
284 };
285
286 enum msp_data_xfer_width {
287 MSP_DATA_TRANSFER_WIDTH_BYTE,
288 MSP_DATA_TRANSFER_WIDTH_HALFWORD,
289 MSP_DATA_TRANSFER_WIDTH_WORD
290 };
291
292 enum msp_frame_sync {
293 MSP_FSYNC_UNIGNORE = 0,
294 MSP_FSYNC_IGNORE = 1,
295 };
296
297 enum msp_phase2_start_mode {
298 MSP_PHASE2_START_MODE_IMEDIATE,
299 MSP_PHASE2_START_MODE_FSYNC
300 };
301
302 enum msp_btf {
303 MSP_BTF_MS_BIT_FIRST = 0,
304 MSP_BTF_LS_BIT_FIRST = 1
305 };
306
307 enum msp_fsync_pol {
308 MSP_FSYNC_POL_ACT_HI = 0,
309 MSP_FSYNC_POL_ACT_LO = 1
310 };
311
312 /* Data delay (in bit clock cycles) */
313 enum msp_delay {
314 MSP_DELAY_0 = 0,
315 MSP_DELAY_1 = 1,
316 MSP_DELAY_2 = 2,
317 MSP_DELAY_3 = 3
318 };
319
320 /* Configurations of clocks (transmit, receive or sample rate generator) */
321 enum msp_edge {
322 MSP_FALLING_EDGE = 0,
323 MSP_RISING_EDGE = 1,
324 };
325
326 enum msp_hws {
327 MSP_SWAP_NONE = 0,
328 MSP_SWAP_BYTE_PER_WORD = 1,
329 MSP_SWAP_BYTE_PER_HALF_WORD = 2,
330 MSP_SWAP_HALF_WORD_PER_WORD = 3
331 };
332
333 enum msp_compress_mode {
334 MSP_COMPRESS_MODE_LINEAR = 0,
335 MSP_COMPRESS_MODE_MU_LAW = 2,
336 MSP_COMPRESS_MODE_A_LAW = 3
337 };
338
339 enum msp_expand_mode {
340 MSP_EXPAND_MODE_LINEAR = 0,
341 MSP_EXPAND_MODE_LINEAR_SIGNED = 1,
342 MSP_EXPAND_MODE_MU_LAW = 2,
343 MSP_EXPAND_MODE_A_LAW = 3
344 };
345
346 #define MSP_FRAME_PERIOD_IN_MONO_MODE 256
347 #define MSP_FRAME_PERIOD_IN_STEREO_MODE 32
348 #define MSP_FRAME_WIDTH_IN_STEREO_MODE 16
349
350 enum msp_protocol {
351 MSP_I2S_PROTOCOL,
352 MSP_PCM_PROTOCOL,
353 MSP_PCM_COMPAND_PROTOCOL,
354 MSP_INVALID_PROTOCOL
355 };
356
357 /*
358 * No of registers to backup during
359 * suspend resume
360 */
361 #define MAX_MSP_BACKUP_REGS 36
362
363 enum i2s_direction_t {
364 MSP_DIR_TX = 0x01,
365 MSP_DIR_RX = 0x02,
366 };
367
368 enum msp_data_size {
369 MSP_DATA_BITS_DEFAULT = -1,
370 MSP_DATA_BITS_8 = 0x00,
371 MSP_DATA_BITS_10,
372 MSP_DATA_BITS_12,
373 MSP_DATA_BITS_14,
374 MSP_DATA_BITS_16,
375 MSP_DATA_BITS_20,
376 MSP_DATA_BITS_24,
377 MSP_DATA_BITS_32,
378 };
379
380 enum msp_state {
381 MSP_STATE_IDLE = 0,
382 MSP_STATE_CONFIGURED = 1,
383 MSP_STATE_RUNNING = 2,
384 };
385
386 enum msp_rx_comparison_enable_mode {
387 MSP_COMPARISON_DISABLED = 0,
388 MSP_COMPARISON_NONEQUAL_ENABLED = 2,
389 MSP_COMPARISON_EQUAL_ENABLED = 3
390 };
391
392 struct msp_multichannel_config {
393 bool rx_multichannel_enable;
394 bool tx_multichannel_enable;
395 enum msp_rx_comparison_enable_mode rx_comparison_enable_mode;
396 u8 padding;
397 u32 comparison_value;
398 u32 comparison_mask;
399 u32 rx_channel_0_enable;
400 u32 rx_channel_1_enable;
401 u32 rx_channel_2_enable;
402 u32 rx_channel_3_enable;
403 u32 tx_channel_0_enable;
404 u32 tx_channel_1_enable;
405 u32 tx_channel_2_enable;
406 u32 tx_channel_3_enable;
407 };
408
409 struct msp_protdesc {
410 u32 rx_phase_mode;
411 u32 tx_phase_mode;
412 u32 rx_phase2_start_mode;
413 u32 tx_phase2_start_mode;
414 u32 rx_byte_order;
415 u32 tx_byte_order;
416 u32 rx_frame_len_1;
417 u32 rx_frame_len_2;
418 u32 tx_frame_len_1;
419 u32 tx_frame_len_2;
420 u32 rx_elem_len_1;
421 u32 rx_elem_len_2;
422 u32 tx_elem_len_1;
423 u32 tx_elem_len_2;
424 u32 rx_data_delay;
425 u32 tx_data_delay;
426 u32 rx_clk_pol;
427 u32 tx_clk_pol;
428 u32 rx_fsync_pol;
429 u32 tx_fsync_pol;
430 u32 rx_half_word_swap;
431 u32 tx_half_word_swap;
432 u32 compression_mode;
433 u32 expansion_mode;
434 u32 frame_sync_ignore;
435 u32 frame_period;
436 u32 frame_width;
437 u32 clocks_per_frame;
438 };
439
440 struct ux500_msp_config {
441 unsigned int f_inputclk;
442 unsigned int rx_clk_sel;
443 unsigned int tx_clk_sel;
444 unsigned int srg_clk_sel;
445 unsigned int rx_fsync_pol;
446 unsigned int tx_fsync_pol;
447 unsigned int rx_fsync_sel;
448 unsigned int tx_fsync_sel;
449 unsigned int rx_fifo_config;
450 unsigned int tx_fifo_config;
451 unsigned int loopback_enable;
452 unsigned int tx_data_enable;
453 unsigned int default_protdesc;
454 struct msp_protdesc protdesc;
455 int multichannel_configured;
456 struct msp_multichannel_config multichannel_config;
457 unsigned int direction;
458 unsigned int protocol;
459 unsigned int frame_freq;
460 enum msp_data_size data_size;
461 unsigned int def_elem_len;
462 unsigned int iodelay;
463 };
464
465 struct ux500_msp {
466 int id;
467 void __iomem *registers;
468 struct device *dev;
469 dma_addr_t tx_rx_addr;
470 enum msp_state msp_state;
471 int def_elem_len;
472 unsigned int dir_busy;
473 int loopback_enable;
474 unsigned int f_bitclk;
475 };
476
477 int ux500_msp_i2s_init_msp(struct platform_device *pdev,
478 struct ux500_msp **msp_p);
479 void ux500_msp_i2s_cleanup_msp(struct platform_device *pdev,
480 struct ux500_msp *msp);
481 int ux500_msp_i2s_open(struct ux500_msp *msp, struct ux500_msp_config *config);
482 int ux500_msp_i2s_close(struct ux500_msp *msp,
483 unsigned int dir);
484 int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd,
485 int direction);
486
487 #endif
488
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