1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copied from the kernel sources to tools/arch/riscv:
4 *
5 * Copyright (C) 2012 ARM Ltd.
6 * Copyright (C) 2013 Regents of the University of California
7 * Copyright (C) 2017 SiFive
8 */
9
10 #ifndef _TOOLS_LINUX_ASM_RISCV_BARRIER_H
11 #define _TOOLS_LINUX_ASM_RISCV_BARRIER_H
12
13 #include <asm/fence.h>
14 #include <linux/compiler.h>
15
16 /* These barriers need to enforce ordering on both devices and memory. */
17 #define mb() RISCV_FENCE(iorw, iorw)
18 #define rmb() RISCV_FENCE(ir, ir)
19 #define wmb() RISCV_FENCE(ow, ow)
20
21 /* These barriers do not need to enforce ordering on devices, just memory. */
22 #define smp_mb() RISCV_FENCE(rw, rw)
23 #define smp_rmb() RISCV_FENCE(r, r)
24 #define smp_wmb() RISCV_FENCE(w, w)
25
26 #define smp_store_release(p, v) \
27 do { \
28 RISCV_FENCE(rw, w); \
29 WRITE_ONCE(*p, v); \
30 } while (0)
31
32 #define smp_load_acquire(p) \
33 ({ \
34 typeof(*p) ___p1 = READ_ONCE(*p); \
35 RISCV_FENCE(r, rw); \
36 ___p1; \
37 })
38
39 #endif /* _TOOLS_LINUX_ASM_RISCV_BARRIER_H */
40
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