1 [
2 {
3 "ArchStdEvent": "SW_INCR",
4 "PublicDescription": "Counts software writes to the PMSWINC_EL0 (software PMU increment) register. The PMSWINC_EL0 register is a manually updated counter for use by application software.\n\nThis event could be used to measure any user program event, such as accesses to a particular data structure (by writing to the PMSWINC_EL0 register each time the data structure is accessed).\n\nTo use the PMSWINC_EL0 register and event, developers must insert instructions that write to the PMSWINC_EL0 register into the source code.\n\nSince the SW_INCR event records writes to the PMSWINC_EL0 register, there is no need to do a read/increment/write sequence to the PMSWINC_EL0 register."
5 },
6 {
7 "ArchStdEvent": "INST_RETIRED",
8 "PublicDescription": "Counts instructions that have been architecturally executed."
9 },
10 {
11 "ArchStdEvent": "CID_WRITE_RETIRED",
12 "PublicDescription": "Counts architecturally executed writes to the CONTEXTIDR register, which usually contain the kernel PID and can be output with hardware trace."
13 },
14 {
15 "ArchStdEvent": "TTBR_WRITE_RETIRED",
16 "PublicDescription": "Counts architectural writes to TTBR0/1_EL1. If virtualization host extensions are enabled (by setting the HCR_EL2.E2H bit to 1), then accesses to TTBR0/1_EL1 that are redirected to TTBR0/1_EL2, or accesses to TTBR0/1_EL12, are counted. TTBRn registers are typically updated when the kernel is swapping user-space threads or applications."
17 },
18 {
19 "ArchStdEvent": "BR_RETIRED",
20 "PublicDescription": "Counts architecturally executed branches, whether the branch is taken or not. Instructions that explicitly write to the PC are also counted."
21 },
22 {
23 "ArchStdEvent": "BR_MIS_PRED_RETIRED",
24 "PublicDescription": "Counts branches counted by BR_RETIRED which were mispredicted and caused a pipeline flush."
25 },
26 {
27 "ArchStdEvent": "OP_RETIRED",
28 "PublicDescription": "Counts micro-operations that are architecturally executed. This is a count of number of micro-operations retired from the commit queue in a single cycle."
29 }
30 ]
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