1 [
2 {
3 "BriefDescription": "% of finished branches that were treated as BC+8",
4 "MetricExpr": "PM_BR_BC_8_CONV / PM_BRU_FIN * 100",
5 "MetricGroup": "branch_prediction",
6 "MetricName": "bc_8_branch_ratio_percent"
7 },
8 {
9 "BriefDescription": "% of finished branches that were pairable but not treated as BC+8",
10 "MetricExpr": "PM_BR_BC_8 / PM_BRU_FIN * 100",
11 "MetricGroup": "branch_prediction",
12 "MetricName": "bc_8_not_converted_branch_ratio_percent"
13 },
14 {
15 "BriefDescription": "Percent of mispredicted branches out of all predicted (correctly and incorrectly) branches that completed",
16 "MetricExpr": "PM_BR_MPRED_CMPL / (PM_BR_PRED_BR0 + PM_BR_PRED_BR1) * 100",
17 "MetricGroup": "branch_prediction",
18 "MetricName": "br_misprediction_percent"
19 },
20 {
21 "BriefDescription": "% of Branch miss predictions per instruction",
22 "MetricExpr": "PM_BR_MPRED_CMPL / PM_RUN_INST_CMPL * 100",
23 "MetricGroup": "branch_prediction",
24 "MetricName": "branch_mispredict_rate_percent"
25 },
26 {
27 "BriefDescription": "Count cache branch misprediction per instruction",
28 "MetricExpr": "PM_BR_MPRED_CCACHE / PM_RUN_INST_CMPL * 100",
29 "MetricGroup": "branch_prediction",
30 "MetricName": "ccache_mispredict_rate_percent"
31 },
32 {
33 "BriefDescription": "Percent of count catch mispredictions out of all completed branches that required count cache predictionn",
34 "MetricExpr": "PM_BR_MPRED_CCACHE / (PM_BR_PRED_CCACHE_BR0 + PM_BR_PRED_CCACHE_BR1) * 100",
35 "MetricGroup": "branch_prediction",
36 "MetricName": "ccache_misprediction_percent"
37 },
38 {
39 "BriefDescription": "CR MisPredictions per Instruction",
40 "MetricExpr": "PM_BR_MPRED_CR / PM_RUN_INST_CMPL * 100",
41 "MetricGroup": "branch_prediction",
42 "MetricName": "cr_mispredict_rate_percent"
43 },
44 {
45 "BriefDescription": "Link stack branch misprediction",
46 "MetricExpr": "(PM_BR_MPRED_TA - PM_BR_MPRED_CCACHE) / PM_RUN_INST_CMPL * 100",
47 "MetricGroup": "branch_prediction",
48 "MetricName": "lstack_mispredict_rate_percent"
49 },
50 {
51 "BriefDescription": "Percent of link stack mispredictions out of all completed branches that required link stack prediction",
52 "MetricExpr": "(PM_BR_MPRED_TA - PM_BR_MPRED_CCACHE) / (PM_BR_PRED_LSTACK_BR0 + PM_BR_PRED_LSTACK_BR1) * 100",
53 "MetricGroup": "branch_prediction",
54 "MetricName": "lstack_misprediction_percent"
55 },
56 {
57 "BriefDescription": "TA MisPredictions per Instruction",
58 "MetricExpr": "PM_BR_MPRED_TA / PM_RUN_INST_CMPL * 100",
59 "MetricGroup": "branch_prediction",
60 "MetricName": "ta_mispredict_rate_percent"
61 },
62 {
63 "BriefDescription": "Percent of target address mispredictions out of all completed branches that required address prediction",
64 "MetricExpr": "PM_BR_MPRED_TA / (PM_BR_PRED_CCACHE_BR0 + PM_BR_PRED_CCACHE_BR1 + PM_BR_PRED_LSTACK_BR0 + PM_BR_PRED_LSTACK_BR1) * 100",
65 "MetricGroup": "branch_prediction",
66 "MetricName": "ta_misprediction_percent"
67 },
68 {
69 "BriefDescription": "Percent of branches completed that were taken",
70 "MetricExpr": "PM_BR_TAKEN_CMPL * 100 / PM_BR_CMPL",
71 "MetricGroup": "branch_prediction",
72 "MetricName": "taken_branches_percent"
73 },
74 {
75 "BriefDescription": "Percent of chip+group+sys pumps that were incorrectly predicted",
76 "MetricExpr": "PM_PUMP_MPRED * 100 / (PM_PUMP_CPRED + PM_PUMP_MPRED)",
77 "MetricGroup": "bus_stats",
78 "MetricName": "any_pump_mpred_percent"
79 },
80 {
81 "BriefDescription": "Percent of chip pumps that were correctly predicted as chip pumps the first time",
82 "MetricExpr": "PM_CHIP_PUMP_CPRED * 100 / PM_L2_CHIP_PUMP",
83 "MetricGroup": "bus_stats",
84 "MetricName": "chip_pump_cpred_percent"
85 },
86 {
87 "BriefDescription": "Percent of group pumps that were correctly predicted as group pumps the first time",
88 "MetricExpr": "PM_GRP_PUMP_CPRED * 100 / PM_L2_GROUP_PUMP",
89 "MetricGroup": "bus_stats",
90 "MetricName": "group_pump_cpred_percent"
91 },
92 {
93 "BriefDescription": "Percent of system pumps that were correctly predicted as group pumps the first time",
94 "MetricExpr": "PM_SYS_PUMP_CPRED * 100 / PM_L2_GROUP_PUMP",
95 "MetricGroup": "bus_stats",
96 "MetricName": "sys_pump_cpred_percent"
97 },
98 {
99 "BriefDescription": "Cycles stalled due to CRU or BRU operations",
100 "MetricExpr": "PM_CMPLU_STALL_BRU_CRU / PM_RUN_INST_CMPL",
101 "MetricGroup": "cpi_breakdown",
102 "MetricName": "bru_cru_stall_cpi"
103 },
104 {
105 "BriefDescription": "Cycles stalled due to ISU Branch Operations",
106 "MetricExpr": "PM_CMPLU_STALL_BRU / PM_RUN_INST_CMPL",
107 "MetricGroup": "cpi_breakdown",
108 "MetricName": "bru_stall_cpi"
109 },
110 {
111 "BriefDescription": "Cycles in which a Group Completed",
112 "MetricExpr": "PM_GRP_CMPL / PM_RUN_INST_CMPL",
113 "MetricGroup": "cpi_breakdown",
114 "MetricName": "completion_cpi"
115 },
116 {
117 "BriefDescription": "Cycles stalled by CO queue full",
118 "MetricExpr": "PM_CMPLU_STALL_COQ_FULL / PM_RUN_INST_CMPL",
119 "MetricGroup": "cpi_breakdown",
120 "MetricName": "coq_full_stall_cpi"
121 },
122 {
123 "BriefDescription": "Cycles stalled due to CRU Operations",
124 "MetricExpr": "(PM_CMPLU_STALL_BRU_CRU - PM_CMPLU_STALL_BRU) / PM_RUN_INST_CMPL",
125 "MetricGroup": "cpi_breakdown",
126 "MetricName": "cru_stall_cpi"
127 },
128 {
129 "BriefDescription": "Cycles stalled by flushes",
130 "MetricExpr": "PM_CMPLU_STALL_FLUSH / PM_RUN_INST_CMPL",
131 "MetricGroup": "cpi_breakdown",
132 "MetricName": "flush_stall_cpi"
133 },
134 {
135 "BriefDescription": "Cycles stalled by FXU Multi-Cycle Instructions",
136 "MetricExpr": "PM_CMPLU_STALL_FXLONG / PM_RUN_INST_CMPL",
137 "MetricGroup": "cpi_breakdown",
138 "MetricName": "fxu_multi_cyc_cpi"
139 },
140 {
141 "BriefDescription": "Cycles stalled by FXU",
142 "MetricExpr": "PM_CMPLU_STALL_FXU / PM_RUN_INST_CMPL",
143 "MetricGroup": "cpi_breakdown",
144 "MetricName": "fxu_stall_cpi"
145 },
146 {
147 "BriefDescription": "Other cycles stalled by FXU",
148 "MetricExpr": "(PM_CMPLU_STALL_FXU / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_FXLONG / PM_RUN_INST_CMPL)",
149 "MetricGroup": "cpi_breakdown",
150 "MetricName": "fxu_stall_other_cpi"
151 },
152 {
153 "BriefDescription": "Cycles GCT empty due to Branch Mispredicts",
154 "MetricExpr": "PM_GCT_NOSLOT_BR_MPRED / PM_RUN_INST_CMPL",
155 "MetricGroup": "cpi_breakdown",
156 "MetricName": "gct_empty_br_mpred_cpi"
157 },
158 {
159 "BriefDescription": "Cycles GCT empty due to Branch Mispredicts and Icache Misses",
160 "MetricExpr": "PM_GCT_NOSLOT_BR_MPRED_ICMISS / PM_RUN_INST_CMPL",
161 "MetricGroup": "cpi_breakdown",
162 "MetricName": "gct_empty_br_mpred_ic_miss_cpi"
163 },
164 {
165 "BriefDescription": "GCT empty cycles",
166 "MetricExpr": "PM_GCT_NOSLOT_CYC / PM_RUN_INST_CMPL",
167 "MetricGroup": "cpi_breakdown",
168 "MetricName": "gct_empty_cpi"
169 },
170 {
171 "BriefDescription": "Cycles GCT empty where dispatch was held",
172 "MetricExpr": "(PM_GCT_NOSLOT_DISP_HELD_MAP + PM_GCT_NOSLOT_DISP_HELD_SRQ + PM_GCT_NOSLOT_DISP_HELD_ISSQ + PM_GCT_NOSLOT_DISP_HELD_OTHER) / PM_RUN_INST_CMPL",
173 "MetricGroup": "cpi_breakdown",
174 "MetricName": "gct_empty_disp_held_cpi"
175 },
176 {
177 "BriefDescription": "Cycles GCT empty where dispatch was held due to issue queue",
178 "MetricExpr": "PM_GCT_NOSLOT_DISP_HELD_ISSQ / PM_RUN_INST_CMPL",
179 "MetricGroup": "cpi_breakdown",
180 "MetricName": "gct_empty_disp_held_issq_cpi"
181 },
182 {
183 "BriefDescription": "Cycles GCT empty where dispatch was held due to maps",
184 "MetricExpr": "PM_GCT_NOSLOT_DISP_HELD_MAP / PM_RUN_INST_CMPL",
185 "MetricGroup": "cpi_breakdown",
186 "MetricName": "gct_empty_disp_held_map_cpi"
187 },
188 {
189 "BriefDescription": "Cycles GCT empty where dispatch was held due to syncs and other effects",
190 "MetricExpr": "PM_GCT_NOSLOT_DISP_HELD_OTHER / PM_RUN_INST_CMPL",
191 "MetricGroup": "cpi_breakdown",
192 "MetricName": "gct_empty_disp_held_other_cpi"
193 },
194 {
195 "BriefDescription": "Cycles GCT empty where dispatch was held due to SRQ",
196 "MetricExpr": "PM_GCT_NOSLOT_DISP_HELD_SRQ / PM_RUN_INST_CMPL",
197 "MetricGroup": "cpi_breakdown",
198 "MetricName": "gct_empty_disp_held_srq_cpi"
199 },
200 {
201 "BriefDescription": "Cycles stalled by GCT empty due to Icache misses",
202 "MetricExpr": "PM_GCT_NOSLOT_IC_MISS / PM_RUN_INST_CMPL",
203 "MetricGroup": "cpi_breakdown",
204 "MetricName": "gct_empty_ic_miss_cpi"
205 },
206 {
207 "BriefDescription": "Cycles stalled by GCT empty due to Icache misses that resolve in the local L2 or L3",
208 "MetricExpr": "(PM_GCT_NOSLOT_IC_MISS - PM_GCT_NOSLOT_IC_L3MISS) / PM_RUN_INST_CMPL",
209 "MetricGroup": "cpi_breakdown",
210 "MetricName": "gct_empty_ic_miss_l2l3_cpi"
211 },
212 {
213 "BriefDescription": "Cycles stalled by GCT empty due to Icache misses that resolve off-chip",
214 "MetricExpr": "PM_GCT_NOSLOT_IC_L3MISS / PM_RUN_INST_CMPL",
215 "MetricGroup": "cpi_breakdown",
216 "MetricName": "gct_empty_ic_miss_l3miss_cpi"
217 },
218 {
219 "BriefDescription": "Other GCT empty cycles",
220 "MetricExpr": "(PM_GCT_NOSLOT_CYC / PM_RUN_INST_CMPL) - (PM_GCT_NOSLOT_IC_MISS / PM_RUN_INST_CMPL) - (PM_GCT_NOSLOT_BR_MPRED / PM_RUN_INST_CMPL) - (PM_GCT_NOSLOT_BR_MPRED_ICMISS / PM_RUN_INST_CMPL) - ((PM_GCT_NOSLOT_DISP_HELD_MAP / PM_RUN_INST_CMPL) + (PM_GCT_NOSLOT_DISP_HELD_SRQ / PM_RUN_INST_CMPL) + (PM_GCT_NOSLOT_DISP_HELD_ISSQ / PM_RUN_INST_CMPL) + (PM_GCT_NOSLOT_DISP_HELD_OTHER / PM_RUN_INST_CMPL))",
221 "MetricGroup": "cpi_breakdown",
222 "MetricName": "gct_empty_other_cpi"
223 },
224 {
225 "BriefDescription": "Cycles stalled by heavyweight syncs",
226 "MetricExpr": "PM_CMPLU_STALL_HWSYNC / PM_RUN_INST_CMPL",
227 "MetricGroup": "cpi_breakdown",
228 "MetricName": "hwsync_stall_cpi"
229 },
230 {
231 "BriefDescription": "Cycles stalled by LSU",
232 "MetricExpr": "PM_CMPLU_STALL_LSU / PM_RUN_INST_CMPL",
233 "MetricGroup": "cpi_breakdown",
234 "MetricName": "lsu_stall_cpi"
235 },
236 {
237 "BriefDescription": "Cycles stalled by D-Cache Misses",
238 "MetricExpr": "PM_CMPLU_STALL_DCACHE_MISS / PM_RUN_INST_CMPL",
239 "MetricGroup": "cpi_breakdown",
240 "MetricName": "lsu_stall_dcache_miss_cpi"
241 },
242 {
243 "BriefDescription": "Cycles stalled by D-Cache Misses that resolved in distant interventions and memory",
244 "MetricExpr": "(PM_CMPLU_STALL_DMISS_L3MISS - PM_CMPLU_STALL_DMISS_LMEM - PM_CMPLU_STALL_DMISS_L21_L31 - PM_CMPLU_STALL_DMISS_REMOTE) / PM_RUN_INST_CMPL",
245 "MetricGroup": "cpi_breakdown",
246 "MetricName": "lsu_stall_dcache_miss_distant_cpi"
247 },
248 {
249 "BriefDescription": "Cycles stalled by D-Cache Misses that resolved in remote or distant caches",
250 "MetricExpr": "PM_CMPLU_STALL_DMISS_L21_L31 / PM_RUN_INST_CMPL",
251 "MetricGroup": "cpi_breakdown",
252 "MetricName": "lsu_stall_dcache_miss_l21l31_cpi"
253 },
254 {
255 "BriefDescription": "Cycles stalled by D-Cache Misses that resolved in the local L2 or L3, where there was a conflict",
256 "MetricExpr": "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT / PM_RUN_INST_CMPL",
257 "MetricGroup": "cpi_breakdown",
258 "MetricName": "lsu_stall_dcache_miss_l2l3_conflict_cpi"
259 },
260 {
261 "BriefDescription": "Cycles stalled by D-Cache Misses that resolved in the local L2 or L3",
262 "MetricExpr": "PM_CMPLU_STALL_DMISS_L2L3 / PM_RUN_INST_CMPL",
263 "MetricGroup": "cpi_breakdown",
264 "MetricName": "lsu_stall_dcache_miss_l2l3_cpi"
265 },
266 {
267 "BriefDescription": "Cycles stalled by D-Cache Misses that resolved in the local L2 or L3, where there was no conflict",
268 "MetricExpr": "(PM_CMPLU_STALL_DMISS_L2L3 - PM_CMPLU_STALL_DMISS_L2L3_CONFLICT) / PM_RUN_INST_CMPL",
269 "MetricGroup": "cpi_breakdown",
270 "MetricName": "lsu_stall_dcache_miss_l2l3_noconflict_cpi"
271 },
272 {
273 "BriefDescription": "Cycles stalled by D-Cache Misses that resolved in other core's caches or memory",
274 "MetricExpr": "PM_CMPLU_STALL_DMISS_L3MISS / PM_RUN_INST_CMPL",
275 "MetricGroup": "cpi_breakdown",
276 "MetricName": "lsu_stall_dcache_miss_l3miss_cpi"
277 },
278 {
279 "BriefDescription": "Cycles stalled by D-Cache Misses that resolved in local memory or local L4",
280 "MetricExpr": "PM_CMPLU_STALL_DMISS_LMEM / PM_RUN_INST_CMPL",
281 "MetricGroup": "cpi_breakdown",
282 "MetricName": "lsu_stall_dcache_miss_lmem_cpi"
283 },
284 {
285 "BriefDescription": "Cycles stalled by D-Cache Misses that resolved in remote interventions and memory",
286 "MetricExpr": "PM_CMPLU_STALL_DMISS_REMOTE / PM_RUN_INST_CMPL",
287 "MetricGroup": "cpi_breakdown",
288 "MetricName": "lsu_stall_dcache_miss_remote_cpi"
289 },
290 {
291 "BriefDescription": "Cycles stalled by ERAT Translation rejects",
292 "MetricExpr": "PM_CMPLU_STALL_ERAT_MISS / PM_RUN_INST_CMPL",
293 "MetricGroup": "cpi_breakdown",
294 "MetricName": "lsu_stall_erat_miss_cpi"
295 },
296 {
297 "BriefDescription": "Cycles stalled by LSU load finishes",
298 "MetricExpr": "PM_CMPLU_STALL_LOAD_FINISH / PM_RUN_INST_CMPL",
299 "MetricGroup": "cpi_breakdown",
300 "MetricName": "lsu_stall_ld_fin_cpi"
301 },
302 {
303 "BriefDescription": "Cycles stalled by LHS rejects",
304 "MetricExpr": "PM_CMPLU_STALL_REJECT_LHS / PM_RUN_INST_CMPL",
305 "MetricGroup": "cpi_breakdown",
306 "MetricName": "lsu_stall_lhs_cpi"
307 },
308 {
309 "BriefDescription": "Cycles stalled by LMQ Full rejects",
310 "MetricExpr": "PM_CMPLU_STALL_REJ_LMQ_FULL / PM_RUN_INST_CMPL",
311 "MetricGroup": "cpi_breakdown",
312 "MetricName": "lsu_stall_lmq_full_cpi"
313 },
314 {
315 "BriefDescription": "Cycles stalled by Other LSU Operations",
316 "MetricExpr": "(PM_CMPLU_STALL_LSU / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_DCACHE_MISS / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_REJECT / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_STORE / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_LOAD_FINISH / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_ST_FWD / PM_RUN_INST_CMPL)",
317 "MetricGroup": "cpi_breakdown",
318 "MetricName": "lsu_stall_other_cpi"
319 },
320 {
321 "BriefDescription": "Cycles stalled by LSU Rejects",
322 "MetricExpr": "PM_CMPLU_STALL_REJECT / PM_RUN_INST_CMPL",
323 "MetricGroup": "cpi_breakdown",
324 "MetricName": "lsu_stall_reject_cpi"
325 },
326 {
327 "BriefDescription": "Cycles stalled by Other LSU Rejects",
328 "MetricExpr": "(PM_CMPLU_STALL_REJECT / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_REJECT_LHS / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_ERAT_MISS / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_REJ_LMQ_FULL / PM_RUN_INST_CMPL)",
329 "MetricGroup": "cpi_breakdown",
330 "MetricName": "lsu_stall_reject_other_cpi"
331 },
332 {
333 "BriefDescription": "Cycles stalled by LSU store forwarding",
334 "MetricExpr": "PM_CMPLU_STALL_ST_FWD / PM_RUN_INST_CMPL",
335 "MetricGroup": "cpi_breakdown",
336 "MetricName": "lsu_stall_st_fwd_cpi"
337 },
338 {
339 "BriefDescription": "Cycles stalled by LSU Stores",
340 "MetricExpr": "PM_CMPLU_STALL_STORE / PM_RUN_INST_CMPL",
341 "MetricGroup": "cpi_breakdown",
342 "MetricName": "lsu_stall_store_cpi"
343 },
344 {
345 "BriefDescription": "Cycles stalled by lightweight syncs",
346 "MetricExpr": "PM_CMPLU_STALL_LWSYNC / PM_RUN_INST_CMPL",
347 "MetricGroup": "cpi_breakdown",
348 "MetricName": "lwsync_stall_cpi"
349 },
350 {
351 "MetricExpr": "PM_CMPLU_STALL_MEM_ECC_DELAY / PM_RUN_INST_CMPL",
352 "MetricGroup": "cpi_breakdown",
353 "MetricName": "mem_ecc_delay_stall_cpi"
354 },
355 {
356 "BriefDescription": "Cycles stalled by nops (nothing next to finish)",
357 "MetricExpr": "PM_CMPLU_STALL_NO_NTF / PM_RUN_INST_CMPL",
358 "MetricGroup": "cpi_breakdown",
359 "MetricName": "no_ntf_stall_cpi"
360 },
361 {
362 "MetricExpr": "PM_NTCG_ALL_FIN / PM_RUN_INST_CMPL",
363 "MetricGroup": "cpi_breakdown",
364 "MetricName": "ntcg_all_fin_cpi"
365 },
366 {
367 "MetricExpr": "PM_CMPLU_STALL_NTCG_FLUSH / PM_RUN_INST_CMPL",
368 "MetricGroup": "cpi_breakdown",
369 "MetricName": "ntcg_flush_cpi"
370 },
371 {
372 "BriefDescription": "Other thread block stall cycles",
373 "MetricExpr": "(PM_CMPLU_STALL_THRD - PM_CMPLU_STALL_LWSYNC - PM_CMPLU_STALL_HWSYNC - PM_CMPLU_STALL_MEM_ECC_DELAY - PM_CMPLU_STALL_FLUSH - PM_CMPLU_STALL_COQ_FULL) / PM_RUN_INST_CMPL",
374 "MetricGroup": "cpi_breakdown",
375 "MetricName": "other_block_stall_cpi"
376 },
377 {
378 "BriefDescription": "Cycles unaccounted for",
379 "MetricExpr": "(PM_RUN_CYC / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL / PM_RUN_INST_CMPL) - (PM_GCT_NOSLOT_CYC / PM_RUN_INST_CMPL) - (PM_NTCG_ALL_FIN / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_THRD / PM_RUN_INST_CMPL) - (PM_GRP_CMPL / PM_RUN_INST_CMPL)",
380 "MetricGroup": "cpi_breakdown",
381 "MetricName": "other_cpi"
382 },
383 {
384 "BriefDescription": "Stall cycles unaccounted for",
385 "MetricExpr": "(PM_CMPLU_STALL / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_BRU_CRU / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_FXU / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_VSU / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_LSU / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_NTCG_FLUSH / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_NO_NTF / PM_RUN_INST_CMPL)",
386 "MetricGroup": "cpi_breakdown",
387 "MetricName": "other_stall_cpi"
388 },
389 {
390 "BriefDescription": "Run cycles per run instruction",
391 "MetricExpr": "PM_RUN_CYC / PM_RUN_INST_CMPL",
392 "MetricGroup": "cpi_breakdown",
393 "MetricName": "run_cpi"
394 },
395 {
396 "BriefDescription": "Completion Stall Cycles",
397 "MetricExpr": "PM_CMPLU_STALL / PM_RUN_INST_CMPL",
398 "MetricGroup": "cpi_breakdown",
399 "MetricName": "stall_cpi"
400 },
401 {
402 "BriefDescription": "Cycles a thread was blocked",
403 "MetricExpr": "PM_CMPLU_STALL_THRD / PM_RUN_INST_CMPL",
404 "MetricGroup": "cpi_breakdown",
405 "MetricName": "thread_block_stall_cpi"
406 },
407 {
408 "BriefDescription": "Cycles stalled by VSU",
409 "MetricExpr": "PM_CMPLU_STALL_VSU / PM_RUN_INST_CMPL",
410 "MetricGroup": "cpi_breakdown",
411 "MetricName": "vsu_stall_cpi"
412 },
413 {
414 "BriefDescription": "Cycles stalled by other VSU Operations",
415 "MetricExpr": "(PM_CMPLU_STALL_VSU - PM_CMPLU_STALL_VECTOR - PM_CMPLU_STALL_SCALAR) / PM_RUN_INST_CMPL",
416 "MetricGroup": "cpi_breakdown",
417 "MetricName": "vsu_stall_other_cpi"
418 },
419 {
420 "BriefDescription": "Cycles stalled by VSU Scalar Operations",
421 "MetricExpr": "PM_CMPLU_STALL_SCALAR / PM_RUN_INST_CMPL",
422 "MetricGroup": "cpi_breakdown",
423 "MetricName": "vsu_stall_scalar_cpi"
424 },
425 {
426 "BriefDescription": "Cycles stalled by VSU Scalar Long Operations",
427 "MetricExpr": "PM_CMPLU_STALL_SCALAR_LONG / PM_RUN_INST_CMPL",
428 "MetricGroup": "cpi_breakdown",
429 "MetricName": "vsu_stall_scalar_long_cpi"
430 },
431 {
432 "BriefDescription": "Cycles stalled by Other VSU Scalar Operations",
433 "MetricExpr": "(PM_CMPLU_STALL_SCALAR / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_SCALAR_LONG / PM_RUN_INST_CMPL)",
434 "MetricGroup": "cpi_breakdown",
435 "MetricName": "vsu_stall_scalar_other_cpi"
436 },
437 {
438 "BriefDescription": "Cycles stalled by VSU Vector Operations",
439 "MetricExpr": "PM_CMPLU_STALL_VECTOR / PM_RUN_INST_CMPL",
440 "MetricGroup": "cpi_breakdown",
441 "MetricName": "vsu_stall_vector_cpi"
442 },
443 {
444 "BriefDescription": "Cycles stalled by VSU Vector Long Operations",
445 "MetricExpr": "PM_CMPLU_STALL_VECTOR_LONG / PM_RUN_INST_CMPL",
446 "MetricGroup": "cpi_breakdown",
447 "MetricName": "vsu_stall_vector_long_cpi"
448 },
449 {
450 "BriefDescription": "Cycles stalled by other VSU Vector Operations",
451 "MetricExpr": "(PM_CMPLU_STALL_VECTOR - PM_CMPLU_STALL_VECTOR_LONG) / PM_RUN_INST_CMPL",
452 "MetricGroup": "cpi_breakdown",
453 "MetricName": "vsu_stall_vector_other_cpi"
454 },
455 {
456 "BriefDescription": "% of DL1 Reloads from Distant L2 or L3 (Modified) per Inst",
457 "MetricExpr": "PM_DATA_FROM_DL2L3_MOD * 100 / PM_RUN_INST_CMPL",
458 "MetricGroup": "dl1_reloads_percent_per_inst",
459 "MetricName": "dl1_reload_from_dl2l3_mod_rate_percent"
460 },
461 {
462 "BriefDescription": "% of DL1 Reloads from Distant L2 or L3 (Shared) per Inst",
463 "MetricExpr": "PM_DATA_FROM_DL2L3_SHR * 100 / PM_RUN_INST_CMPL",
464 "MetricGroup": "dl1_reloads_percent_per_inst",
465 "MetricName": "dl1_reload_from_dl2l3_shr_rate_percent"
466 },
467 {
468 "BriefDescription": "% of DL1 Reloads from Distant L4 per Inst",
469 "MetricExpr": "PM_DATA_FROM_DL4 * 100 / PM_RUN_INST_CMPL",
470 "MetricGroup": "dl1_reloads_percent_per_inst",
471 "MetricName": "dl1_reload_from_dl4_rate_percent"
472 },
473 {
474 "BriefDescription": "% of DL1 Reloads from Distant Memory per Inst",
475 "MetricExpr": "PM_DATA_FROM_DMEM * 100 / PM_RUN_INST_CMPL",
476 "MetricGroup": "dl1_reloads_percent_per_inst",
477 "MetricName": "dl1_reload_from_dmem_rate_percent"
478 },
479 {
480 "BriefDescription": "% of DL1 reloads from Private L2, other core per Inst",
481 "MetricExpr": "PM_DATA_FROM_L21_MOD * 100 / PM_RUN_INST_CMPL",
482 "MetricGroup": "dl1_reloads_percent_per_inst",
483 "MetricName": "dl1_reload_from_l21_mod_rate_percent"
484 },
485 {
486 "BriefDescription": "% of DL1 reloads from Private L2, other core per Inst",
487 "MetricExpr": "PM_DATA_FROM_L21_SHR * 100 / PM_RUN_INST_CMPL",
488 "MetricGroup": "dl1_reloads_percent_per_inst",
489 "MetricName": "dl1_reload_from_l21_shr_rate_percent"
490 },
491 {
492 "BriefDescription": "Percentage of L2 load hits per instruction where the L2 experienced a Load-Hit-Store conflict",
493 "MetricExpr": "PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST * 100 / PM_RUN_INST_CMPL",
494 "MetricGroup": "dl1_reloads_percent_per_inst",
495 "MetricName": "dl1_reload_from_l2_lhs_rate_percent"
496 },
497 {
498 "BriefDescription": "% of DL1 reloads from L2 per Inst",
499 "MetricExpr": "PM_DATA_FROM_L2MISS * 100 / PM_RUN_INST_CMPL",
500 "MetricGroup": "dl1_reloads_percent_per_inst",
501 "MetricName": "dl1_reload_from_l2_miss_rate_percent"
502 },
503 {
504 "BriefDescription": "Percentage of L2 load hits per instruction where the L2 did not experience a conflict",
505 "MetricExpr": "PM_DATA_FROM_L2_NO_CONFLICT * 100 / PM_RUN_INST_CMPL",
506 "MetricGroup": "dl1_reloads_percent_per_inst",
507 "MetricName": "dl1_reload_from_l2_no_conflict_rate_percent"
508 },
509 {
510 "BriefDescription": "Percentage of L2 load hits per instruction where the L2 experienced some conflict other than Load-Hit-Store",
511 "MetricExpr": "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER * 100 / PM_RUN_INST_CMPL",
512 "MetricGroup": "dl1_reloads_percent_per_inst",
513 "MetricName": "dl1_reload_from_l2_other_conflict_rate_percent"
514 },
515 {
516 "BriefDescription": "% of DL1 reloads from L2 per Inst",
517 "MetricExpr": "PM_DATA_FROM_L2 * 100 / PM_RUN_INST_CMPL",
518 "MetricGroup": "dl1_reloads_percent_per_inst",
519 "MetricName": "dl1_reload_from_l2_rate_percent"
520 },
521 {
522 "BriefDescription": "% of DL1 reloads from Private L3 M state, other core per Inst",
523 "MetricExpr": "PM_DATA_FROM_L31_MOD * 100 / PM_RUN_INST_CMPL",
524 "MetricGroup": "dl1_reloads_percent_per_inst",
525 "MetricName": "dl1_reload_from_l31_mod_rate_percent"
526 },
527 {
528 "BriefDescription": "% of DL1 reloads from Private L3 S tate, other core per Inst",
529 "MetricExpr": "PM_DATA_FROM_L31_SHR * 100 / PM_RUN_INST_CMPL",
530 "MetricGroup": "dl1_reloads_percent_per_inst",
531 "MetricName": "dl1_reload_from_l31_shr_rate_percent"
532 },
533 {
534 "BriefDescription": "Percentage of L3 load hits per instruction where the load collided with a pending prefetch",
535 "MetricExpr": "PM_DATA_FROM_L3_DISP_CONFLICT * 100 / PM_RUN_INST_CMPL",
536 "MetricGroup": "dl1_reloads_percent_per_inst",
537 "MetricName": "dl1_reload_from_l3_conflict_rate_percent"
538 },
539 {
540 "BriefDescription": "% of DL1 reloads from L3 per Inst",
541 "MetricExpr": "PM_DATA_FROM_L3MISS * 100 / PM_RUN_INST_CMPL",
542 "MetricGroup": "dl1_reloads_percent_per_inst",
543 "MetricName": "dl1_reload_from_l3_miss_rate_percent"
544 },
545 {
546 "BriefDescription": "Percentage of L3 load hits per instruction where the L3 did not experience a conflict",
547 "MetricExpr": "PM_DATA_FROM_L3_NO_CONFLICT * 100 / PM_RUN_INST_CMPL",
548 "MetricGroup": "dl1_reloads_percent_per_inst",
549 "MetricName": "dl1_reload_from_l3_no_conflict_rate_percent"
550 },
551 {
552 "BriefDescription": "% of DL1 Reloads from L3 per Inst",
553 "MetricExpr": "PM_DATA_FROM_L3 * 100 / PM_RUN_INST_CMPL",
554 "MetricGroup": "dl1_reloads_percent_per_inst",
555 "MetricName": "dl1_reload_from_l3_rate_percent"
556 },
557 {
558 "BriefDescription": "% of DL1 Reloads from Local L4 per Inst",
559 "MetricExpr": "PM_DATA_FROM_LL4 * 100 / PM_RUN_INST_CMPL",
560 "MetricGroup": "dl1_reloads_percent_per_inst",
561 "MetricName": "dl1_reload_from_ll4_rate_percent"
562 },
563 {
564 "BriefDescription": "% of DL1 Reloads from Local Memory per Inst",
565 "MetricExpr": "PM_DATA_FROM_LMEM * 100 / PM_RUN_INST_CMPL",
566 "MetricGroup": "dl1_reloads_percent_per_inst",
567 "MetricName": "dl1_reload_from_lmem_rate_percent"
568 },
569 {
570 "BriefDescription": "% of DL1 reloads from Private L3, other core per Inst",
571 "MetricExpr": "PM_DATA_FROM_RL2L3_MOD * 100 / PM_RUN_INST_CMPL",
572 "MetricGroup": "dl1_reloads_percent_per_inst",
573 "MetricName": "dl1_reload_from_rl2l3_mod_rate_percent"
574 },
575 {
576 "BriefDescription": "% of DL1 reloads from Private L3, other core per Inst",
577 "MetricExpr": "PM_DATA_FROM_RL2L3_SHR * 100 / PM_RUN_INST_CMPL",
578 "MetricGroup": "dl1_reloads_percent_per_inst",
579 "MetricName": "dl1_reload_from_rl2l3_shr_rate_percent"
580 },
581 {
582 "BriefDescription": "% of DL1 Reloads from Remote Memory per Inst",
583 "MetricExpr": "PM_DATA_FROM_RL4 * 100 / PM_RUN_INST_CMPL",
584 "MetricGroup": "dl1_reloads_percent_per_inst",
585 "MetricName": "dl1_reload_from_rl4_rate_percent"
586 },
587 {
588 "BriefDescription": "% of DL1 Reloads from Remote Memory per Inst",
589 "MetricExpr": "PM_DATA_FROM_RMEM * 100 / PM_RUN_INST_CMPL",
590 "MetricGroup": "dl1_reloads_percent_per_inst",
591 "MetricName": "dl1_reload_from_rmem_rate_percent"
592 },
593 {
594 "BriefDescription": "Percentage of L1 demand load misses per run instruction",
595 "MetricExpr": "PM_LD_MISS_L1 * 100 / PM_RUN_INST_CMPL",
596 "MetricGroup": "dl1_reloads_percent_per_inst",
597 "MetricName": "l1_ld_miss_rate_percent"
598 },
599 {
600 "BriefDescription": "% of DL1 misses that result in a cache reload",
601 "MetricExpr": "PM_L1_DCACHE_RELOAD_VALID * 100 / PM_LD_MISS_L1",
602 "MetricGroup": "dl1_reloads_percent_per_ref",
603 "MetricName": "dl1_miss_reloads_percent"
604 },
605 {
606 "BriefDescription": "% of DL1 dL1_Reloads from Distant L2 or L3 (Modified)",
607 "MetricExpr": "PM_DATA_FROM_DL2L3_MOD * 100 / PM_L1_DCACHE_RELOAD_VALID",
608 "MetricGroup": "dl1_reloads_percent_per_ref",
609 "MetricName": "dl1_reload_from_dl2l3_mod_percent"
610 },
611 {
612 "BriefDescription": "% of DL1 dL1_Reloads from Distant L2 or L3 (Shared)",
613 "MetricExpr": "PM_DATA_FROM_DL2L3_SHR * 100 / PM_L1_DCACHE_RELOAD_VALID",
614 "MetricGroup": "dl1_reloads_percent_per_ref",
615 "MetricName": "dl1_reload_from_dl2l3_shr_percent"
616 },
617 {
618 "BriefDescription": "% of DL1 dL1_Reloads from Distant L4",
619 "MetricExpr": "PM_DATA_FROM_DL4 * 100 / PM_L1_DCACHE_RELOAD_VALID",
620 "MetricGroup": "dl1_reloads_percent_per_ref",
621 "MetricName": "dl1_reload_from_dl4_percent"
622 },
623 {
624 "BriefDescription": "% of DL1 dL1_Reloads from Distant Memory",
625 "MetricExpr": "PM_DATA_FROM_DMEM * 100 / PM_L1_DCACHE_RELOAD_VALID",
626 "MetricGroup": "dl1_reloads_percent_per_ref",
627 "MetricName": "dl1_reload_from_dmem_percent"
628 },
629 {
630 "BriefDescription": "% of DL1 reloads from Private L2, other core",
631 "MetricExpr": "PM_DATA_FROM_L21_MOD * 100 / PM_L1_DCACHE_RELOAD_VALID",
632 "MetricGroup": "dl1_reloads_percent_per_ref",
633 "MetricName": "dl1_reload_from_l21_mod_percent"
634 },
635 {
636 "BriefDescription": "% of DL1 reloads from Private L2, other core",
637 "MetricExpr": "PM_DATA_FROM_L21_SHR * 100 / PM_L1_DCACHE_RELOAD_VALID",
638 "MetricGroup": "dl1_reloads_percent_per_ref",
639 "MetricName": "dl1_reload_from_l21_shr_percent"
640 },
641 {
642 "BriefDescription": "Percentage of DL1 reloads from L2 with a Load-Hit-Store conflict",
643 "MetricExpr": "PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST * 100 / PM_L1_DCACHE_RELOAD_VALID",
644 "MetricGroup": "dl1_reloads_percent_per_ref",
645 "MetricName": "dl1_reload_from_l2_lhs_percent"
646 },
647 {
648 "BriefDescription": "Percentage of DL1 reloads from L2 with no conflicts",
649 "MetricExpr": "PM_DATA_FROM_L2_NO_CONFLICT * 100 / PM_L1_DCACHE_RELOAD_VALID",
650 "MetricGroup": "dl1_reloads_percent_per_ref",
651 "MetricName": "dl1_reload_from_l2_no_conflict_percent"
652 },
653 {
654 "BriefDescription": "Percentage of DL1 reloads from L2 with some conflict other than Load-Hit-Store",
655 "MetricExpr": "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER * 100 / PM_L1_DCACHE_RELOAD_VALID",
656 "MetricGroup": "dl1_reloads_percent_per_ref",
657 "MetricName": "dl1_reload_from_l2_other_conflict_percent"
658 },
659 {
660 "BriefDescription": "% of DL1 reloads from L2",
661 "MetricExpr": "PM_DATA_FROM_L2 * 100 / PM_L1_DCACHE_RELOAD_VALID",
662 "MetricGroup": "dl1_reloads_percent_per_ref",
663 "MetricName": "dl1_reload_from_l2_percent"
664 },
665 {
666 "BriefDescription": "% of DL1 reloads from Private L3, other core",
667 "MetricExpr": "PM_DATA_FROM_L31_MOD * 100 / PM_L1_DCACHE_RELOAD_VALID",
668 "MetricGroup": "dl1_reloads_percent_per_ref",
669 "MetricName": "dl1_reload_from_l31_mod_percent"
670 },
671 {
672 "BriefDescription": "% of DL1 reloads from Private L3, other core",
673 "MetricExpr": "PM_DATA_FROM_L31_SHR * 100 / PM_L1_DCACHE_RELOAD_VALID",
674 "MetricGroup": "dl1_reloads_percent_per_ref",
675 "MetricName": "dl1_reload_from_l31_shr_percent"
676 },
677 {
678 "BriefDescription": "Percentage of DL1 reloads from L3 where the load collided with a pending prefetch",
679 "MetricExpr": "PM_DATA_FROM_L3_DISP_CONFLICT * 100 / PM_L1_DCACHE_RELOAD_VALID",
680 "MetricGroup": "dl1_reloads_percent_per_ref",
681 "MetricName": "dl1_reload_from_l3_conflict_percent"
682 },
683 {
684 "BriefDescription": "Percentage of L3 load hits per instruction where the line was brought into the L3 by a prefetch operation",
685 "MetricExpr": "PM_DATA_FROM_L3_MEPF * 100 / PM_RUN_INST_CMPL",
686 "MetricGroup": "dl1_reloads_percent_per_ref",
687 "MetricName": "dl1_reload_from_l3_mepf_rate_percent"
688 },
689 {
690 "BriefDescription": "Percentage of DL1 reloads from L3 without conflicts",
691 "MetricExpr": "PM_DATA_FROM_L3_NO_CONFLICT * 100 / PM_L1_DCACHE_RELOAD_VALID",
692 "MetricGroup": "dl1_reloads_percent_per_ref",
693 "MetricName": "dl1_reload_from_l3_no_conflict_percent"
694 },
695 {
696 "BriefDescription": "% of DL1 Reloads from L3",
697 "MetricExpr": "PM_DATA_FROM_L3 * 100 / PM_L1_DCACHE_RELOAD_VALID",
698 "MetricGroup": "dl1_reloads_percent_per_ref",
699 "MetricName": "dl1_reload_from_l3_percent"
700 },
701 {
702 "BriefDescription": "% of DL1 dL1_Reloads from Local L4",
703 "MetricExpr": "PM_DATA_FROM_LL4 * 100 / PM_L1_DCACHE_RELOAD_VALID",
704 "MetricGroup": "dl1_reloads_percent_per_ref",
705 "MetricName": "dl1_reload_from_ll4_percent"
706 },
707 {
708 "BriefDescription": "% of DL1 dL1_Reloads from Local Memory",
709 "MetricExpr": "PM_DATA_FROM_LMEM * 100 / PM_L1_DCACHE_RELOAD_VALID",
710 "MetricGroup": "dl1_reloads_percent_per_ref",
711 "MetricName": "dl1_reload_from_lmem_percent"
712 },
713 {
714 "BriefDescription": "% of DL1 dL1_Reloads from Remote L2 or L3 (Modified)",
715 "MetricExpr": "PM_DATA_FROM_RL2L3_MOD * 100 / PM_L1_DCACHE_RELOAD_VALID",
716 "MetricGroup": "dl1_reloads_percent_per_ref",
717 "MetricName": "dl1_reload_from_rl2l3_mod_percent"
718 },
719 {
720 "BriefDescription": "% of DL1 dL1_Reloads from Remote L2 or L3 (Shared)",
721 "MetricExpr": "PM_DATA_FROM_RL2L3_SHR * 100 / PM_L1_DCACHE_RELOAD_VALID",
722 "MetricGroup": "dl1_reloads_percent_per_ref",
723 "MetricName": "dl1_reload_from_rl2l3_shr_percent"
724 },
725 {
726 "BriefDescription": "% of DL1 dL1_Reloads from Remote L4",
727 "MetricExpr": "PM_DATA_FROM_RL4 * 100 / PM_L1_DCACHE_RELOAD_VALID",
728 "MetricGroup": "dl1_reloads_percent_per_ref",
729 "MetricName": "dl1_reload_from_rl4_percent"
730 },
731 {
732 "BriefDescription": "% of DL1 dL1_Reloads from Remote Memory",
733 "MetricExpr": "PM_DATA_FROM_RMEM * 100 / PM_L1_DCACHE_RELOAD_VALID",
734 "MetricGroup": "dl1_reloads_percent_per_ref",
735 "MetricName": "dl1_reload_from_rmem_percent"
736 },
737 {
738 "BriefDescription": "dL1 miss portion of CPI",
739 "MetricExpr": "( (PM_CMPLU_STALL_DCACHE_MISS / PM_RUN_INST_CMPL)/ (PM_RUN_CYC / PM_RUN_INST_CMPL)) * 100",
740 "MetricGroup": "estimated_dcache_miss_cpi",
741 "MetricName": "dcache_miss_cpi_percent"
742 },
743 {
744 "BriefDescription": "estimate of dl2l3 distant MOD miss rates with measured DL2L3 MOD latency as a %of dcache miss cpi",
745 "MetricExpr": "(((PM_DATA_FROM_DL2L3_MOD / PM_RUN_INST_CMPL) * (PM_MRK_DATA_FROM_DL2L3_MOD_CYC/ PM_MRK_DATA_FROM_DL2L3_MOD)) / (PM_CMPLU_STALL_DCACHE_MISS / PM_RUN_INST_CMPL)) *100",
746 "MetricGroup": "estimated_dcache_miss_cpi",
747 "MetricName": "dl2l3_mod_cpi_percent"
748 },
749 {
750 "BriefDescription": "estimate of dl2l3 distant SHR miss rates with measured DL2L3 SHR latency as a %of dcache miss cpi",
751 "MetricExpr": "(((PM_DATA_FROM_DL2L3_SHR / PM_RUN_INST_CMPL) * (PM_MRK_DATA_FROM_DL2L3_SHR_CYC/ PM_MRK_DATA_FROM_DL2L3_SHR)) / (PM_CMPLU_STALL_DCACHE_MISS / PM_RUN_INST_CMPL)) *100",
752 "MetricGroup": "estimated_dcache_miss_cpi",
753 "MetricName": "dl2l3_shr_cpi_percent"
754 },
755 {
756 "BriefDescription": "estimate of distant L4 miss rates with measured DL4 latency as a %of dcache miss cpi",
757 "MetricExpr": "(((PM_DATA_FROM_DL4 / PM_RUN_INST_CMPL) * (PM_MRK_DATA_FROM_DL4_CYC/ PM_MRK_DATA_FROM_DL4)) / (PM_CMPLU_STALL_DCACHE_MISS / PM_RUN_INST_CMPL)) *100",
758 "MetricGroup": "estimated_dcache_miss_cpi",
759 "MetricName": "dl4_cpi_percent"
760 },
761 {
762 "BriefDescription": "estimate of distant memory miss rates with measured DMEM latency as a %of dcache miss cpi",
763 "MetricExpr": "(((PM_DATA_FROM_DMEM / PM_RUN_INST_CMPL) * (PM_MRK_DATA_FROM_DMEM_CYC/ PM_MRK_DATA_FROM_DMEM)) / (PM_CMPLU_STALL_DCACHE_MISS / PM_RUN_INST_CMPL)) *100",
764 "MetricGroup": "estimated_dcache_miss_cpi",
765 "MetricName": "dmem_cpi_percent"
766 },
767 {
768 "BriefDescription": "estimate of dl21 MOD miss rates with measured L21 MOD latency as a %of dcache miss cpi",
769 "MetricExpr": "(((PM_DATA_FROM_L21_MOD / PM_RUN_INST_CMPL) * (PM_MRK_DATA_FROM_L21_MOD_CYC/ PM_MRK_DATA_FROM_L21_MOD)) / (PM_CMPLU_STALL_DCACHE_MISS / PM_RUN_INST_CMPL)) *100",
770 "MetricGroup": "estimated_dcache_miss_cpi",
771 "MetricName": "l21_mod_cpi_percent"
772 },
773 {
774 "BriefDescription": "estimate of dl21 SHR miss rates with measured L21 SHR latency as a %of dcache miss cpi",
775 "MetricExpr": "(((PM_DATA_FROM_L21_SHR / PM_RUN_INST_CMPL) * (PM_MRK_DATA_FROM_L21_SHR_CYC/ PM_MRK_DATA_FROM_L21_SHR)) / (PM_CMPLU_STALL_DCACHE_MISS / PM_RUN_INST_CMPL)) *100",
776 "MetricGroup": "estimated_dcache_miss_cpi",
777 "MetricName": "l21_shr_cpi_percent"
778 },
779 {
780 "BriefDescription": "estimate of dl2 miss rates with measured L2 latency as a %of dcache miss cpi",
781 "MetricExpr": "(((PM_DATA_FROM_L2 / PM_RUN_INST_CMPL) * (PM_MRK_DATA_FROM_L2_CYC/ PM_MRK_DATA_FROM_L2)) / (PM_CMPLU_STALL_DCACHE_MISS / PM_RUN_INST_CMPL) ) *100",
782 "MetricGroup": "estimated_dcache_miss_cpi",
783 "MetricName": "l2_cpi_percent"
784 },
785 {
786 "BriefDescription": "estimate of dl31 MOD miss rates with measured L31 MOD latency as a %of dcache miss cpi",
787 "MetricExpr": "(((PM_DATA_FROM_L31_MOD / PM_RUN_INST_CMPL) * (PM_MRK_DATA_FROM_L31_MOD_CYC/ PM_MRK_DATA_FROM_L31_MOD)) / (PM_CMPLU_STALL_DCACHE_MISS / PM_RUN_INST_CMPL)) *100",
788 "MetricGroup": "estimated_dcache_miss_cpi",
789 "MetricName": "l31_mod_cpi_percent"
790 },
791 {
792 "BriefDescription": "estimate of dl31 SHR miss rates with measured L31 SHR latency as a %of dcache miss cpi",
793 "MetricExpr": "(((PM_DATA_FROM_L31_SHR / PM_RUN_INST_CMPL) * (PM_MRK_DATA_FROM_L31_SHR_CYC/ PM_MRK_DATA_FROM_L31_SHR)) / (PM_CMPLU_STALL_DCACHE_MISS / PM_RUN_INST_CMPL)) *100",
794 "MetricGroup": "estimated_dcache_miss_cpi",
795 "MetricName": "l31_shr_cpi_percent"
796 },
797 {
798 "BriefDescription": "estimate of dl3 miss rates with measured L3 latency as a % of dcache miss cpi",
799 "MetricExpr": "(((PM_DATA_FROM_L3 / PM_RUN_INST_CMPL) * (PM_MRK_DATA_FROM_L3_CYC/ PM_MRK_DATA_FROM_L3)) / (PM_CMPLU_STALL_DCACHE_MISS / PM_RUN_INST_CMPL)) * 100",
800 "MetricGroup": "estimated_dcache_miss_cpi",
801 "MetricName": "l3_cpi_percent"
802 },
803 {
804 "BriefDescription": "estimate of Local L4 miss rates with measured LL4 latency as a %of dcache miss cpi",
805 "MetricExpr": "(((PM_DATA_FROM_LL4 / PM_RUN_INST_CMPL) * (PM_MRK_DATA_FROM_LL4_CYC/ PM_MRK_DATA_FROM_LL4)) / (PM_CMPLU_STALL_DCACHE_MISS / PM_RUN_INST_CMPL)) *100",
806 "MetricGroup": "estimated_dcache_miss_cpi",
807 "MetricName": "ll4_cpi_percent"
808 },
809 {
810 "BriefDescription": "estimate of Local memory miss rates with measured LMEM latency as a %of dcache miss cpi",
811 "MetricExpr": "(((PM_DATA_FROM_LMEM / PM_RUN_INST_CMPL) * (PM_MRK_DATA_FROM_LMEM_CYC/ PM_MRK_DATA_FROM_LMEM)) / (PM_CMPLU_STALL_DCACHE_MISS / PM_RUN_INST_CMPL)) *100",
812 "MetricGroup": "estimated_dcache_miss_cpi",
813 "MetricName": "lmem_cpi_percent"
814 },
815 {
816 "BriefDescription": "estimate of dl2l3 remote MOD miss rates with measured RL2L3 MOD latency as a %of dcache miss cpi",
817 "MetricExpr": "(((PM_DATA_FROM_RL2L3_MOD / PM_RUN_INST_CMPL) * (PM_MRK_DATA_FROM_RL2L3_MOD_CYC/ PM_MRK_DATA_FROM_RL2L3_MOD)) / (PM_CMPLU_STALL_DCACHE_MISS / PM_RUN_INST_CMPL)) *100",
818 "MetricGroup": "estimated_dcache_miss_cpi",
819 "MetricName": "rl2l3_mod_cpi_percent"
820 },
821 {
822 "BriefDescription": "estimate of dl2l3 shared miss rates with measured RL2L3 SHR latency as a %of dcache miss cpi",
823 "MetricExpr": "(((PM_DATA_FROM_RL2L3_SHR / PM_RUN_INST_CMPL) * (PM_MRK_DATA_FROM_RL2L3_SHR_CYC/ PM_MRK_DATA_FROM_RL2L3_SHR)) / (PM_CMPLU_STALL_DCACHE_MISS / PM_RUN_INST_CMPL)) * 100",
824 "MetricGroup": "estimated_dcache_miss_cpi",
825 "MetricName": "rl2l3_shr_cpi_percent"
826 },
827 {
828 "BriefDescription": "estimate of remote L4 miss rates with measured RL4 latency as a %of dcache miss cpi",
829 "MetricExpr": "(((PM_DATA_FROM_RL4 / PM_RUN_INST_CMPL) * (PM_MRK_DATA_FROM_RL4_CYC/ PM_MRK_DATA_FROM_RL4)) / (PM_CMPLU_STALL_DCACHE_MISS / PM_RUN_INST_CMPL)) *100",
830 "MetricGroup": "estimated_dcache_miss_cpi",
831 "MetricName": "rl4_cpi_percent"
832 },
833 {
834 "BriefDescription": "estimate of remote memory miss rates with measured RMEM latency as a %of dcache miss cpi",
835 "MetricExpr": "(((PM_DATA_FROM_RMEM / PM_RUN_INST_CMPL) * (PM_MRK_DATA_FROM_RMEM_CYC/ PM_MRK_DATA_FROM_RMEM)) / (PM_CMPLU_STALL_DCACHE_MISS / PM_RUN_INST_CMPL)) *100",
836 "MetricGroup": "estimated_dcache_miss_cpi",
837 "MetricName": "rmem_cpi_percent"
838 },
839 {
840 "BriefDescription": "Branch Mispredict flushes per instruction",
841 "MetricExpr": "PM_FLUSH_BR_MPRED / PM_RUN_INST_CMPL * 100",
842 "MetricGroup": "general",
843 "MetricName": "br_mpred_flush_rate_percent"
844 },
845 {
846 "BriefDescription": "Cycles per instruction",
847 "MetricExpr": "PM_CYC / PM_INST_CMPL",
848 "MetricGroup": "general",
849 "MetricName": "cpi"
850 },
851 {
852 "BriefDescription": "Percentage Cycles a group completed",
853 "MetricExpr": "PM_GRP_CMPL / PM_CYC * 100",
854 "MetricGroup": "general",
855 "MetricName": "cyc_grp_completed_percent"
856 },
857 {
858 "BriefDescription": "Percentage Cycles a group dispatched",
859 "MetricExpr": "PM_1PLUS_PPC_DISP / PM_CYC * 100",
860 "MetricGroup": "general",
861 "MetricName": "cyc_grp_dispatched_percent"
862 },
863 {
864 "BriefDescription": "Cycles per group",
865 "MetricExpr": "PM_CYC / PM_1PLUS_PPC_CMPL",
866 "MetricGroup": "general",
867 "MetricName": "cyc_per_group"
868 },
869 {
870 "BriefDescription": "GCT empty cycles",
871 "MetricExpr": "(PM_FLUSH_DISP / PM_RUN_INST_CMPL) * 100",
872 "MetricGroup": "general",
873 "MetricName": "disp_flush_rate_percent"
874 },
875 {
876 "BriefDescription": "% DTLB miss rate per inst",
877 "MetricExpr": "PM_DTLB_MISS / PM_RUN_INST_CMPL *100",
878 "MetricGroup": "general",
879 "MetricName": "dtlb_miss_rate_percent"
880 },
881 {
882 "BriefDescription": "Flush rate (%)",
883 "MetricExpr": "PM_FLUSH * 100 / PM_RUN_INST_CMPL",
884 "MetricGroup": "general",
885 "MetricName": "flush_rate_percent"
886 },
887 {
888 "BriefDescription": "GCT slot utilization (11 to 14) as a % of cycles this thread had at least 1 slot valid",
889 "MetricExpr": "PM_GCT_UTIL_11_14_ENTRIES / ( PM_RUN_CYC - PM_GCT_NOSLOT_CYC) * 100",
890 "MetricGroup": "general",
891 "MetricName": "gct_util_11to14_slots_percent"
892 },
893 {
894 "BriefDescription": "GCT slot utilization (15 to 17) as a % of cycles this thread had at least 1 slot valid",
895 "MetricExpr": "PM_GCT_UTIL_15_17_ENTRIES / ( PM_RUN_CYC - PM_GCT_NOSLOT_CYC) * 100",
896 "MetricGroup": "general",
897 "MetricName": "gct_util_15to17_slots_percent"
898 },
899 {
900 "BriefDescription": "GCT slot utilization 18+ as a % of cycles this thread had at least 1 slot valid",
901 "MetricExpr": "PM_GCT_UTIL_18_ENTRIES / ( PM_RUN_CYC - PM_GCT_NOSLOT_CYC) * 100",
902 "MetricGroup": "general",
903 "MetricName": "gct_util_18plus_slots_percent"
904 },
905 {
906 "BriefDescription": "GCT slot utilization (1 to 2) as a % of cycles this thread had at least 1 slot valid",
907 "MetricExpr": "PM_GCT_UTIL_1_2_ENTRIES / ( PM_RUN_CYC - PM_GCT_NOSLOT_CYC) * 100",
908 "MetricGroup": "general",
909 "MetricName": "gct_util_1to2_slots_percent"
910 },
911 {
912 "BriefDescription": "GCT slot utilization (3 to 6) as a % of cycles this thread had at least 1 slot valid",
913 "MetricExpr": "PM_GCT_UTIL_3_6_ENTRIES / ( PM_RUN_CYC - PM_GCT_NOSLOT_CYC) * 100",
914 "MetricGroup": "general",
915 "MetricName": "gct_util_3to6_slots_percent"
916 },
917 {
918 "BriefDescription": "GCT slot utilization (7 to 10) as a % of cycles this thread had at least 1 slot valid",
919 "MetricExpr": "PM_GCT_UTIL_7_10_ENTRIES / ( PM_RUN_CYC - PM_GCT_NOSLOT_CYC) * 100",
920 "MetricGroup": "general",
921 "MetricName": "gct_util_7to10_slots_percent"
922 },
923 {
924 "BriefDescription": "Avg. group size",
925 "MetricExpr": "PM_INST_CMPL / PM_1PLUS_PPC_CMPL",
926 "MetricGroup": "general",
927 "MetricName": "group_size"
928 },
929 {
930 "BriefDescription": "Instructions per group",
931 "MetricExpr": "PM_INST_CMPL / PM_1PLUS_PPC_CMPL",
932 "MetricGroup": "general",
933 "MetricName": "inst_per_group"
934 },
935 {
936 "BriefDescription": "Instructions per cycles",
937 "MetricExpr": "PM_INST_CMPL / PM_CYC",
938 "MetricGroup": "general",
939 "MetricName": "ipc"
940 },
941 {
942 "BriefDescription": "% ITLB miss rate per inst",
943 "MetricExpr": "PM_ITLB_MISS / PM_RUN_INST_CMPL *100",
944 "MetricGroup": "general",
945 "MetricName": "itlb_miss_rate_percent"
946 },
947 {
948 "BriefDescription": "Percentage of L1 load misses per L1 load ref",
949 "MetricExpr": "PM_LD_MISS_L1 / PM_LD_REF_L1 * 100",
950 "MetricGroup": "general",
951 "MetricName": "l1_ld_miss_ratio_percent"
952 },
953 {
954 "BriefDescription": "Percentage of L1 store misses per run instruction",
955 "MetricExpr": "PM_ST_MISS_L1 * 100 / PM_RUN_INST_CMPL",
956 "MetricGroup": "general",
957 "MetricName": "l1_st_miss_rate_percent"
958 },
959 {
960 "BriefDescription": "Percentage of L1 store misses per L1 store ref",
961 "MetricExpr": "PM_ST_MISS_L1 / PM_ST_FIN * 100",
962 "MetricGroup": "general",
963 "MetricName": "l1_st_miss_ratio_percent"
964 },
965 {
966 "BriefDescription": "L2 Instruction Miss Rate (per instruction)(%)",
967 "MetricExpr": "PM_INST_FROM_L2MISS * 100 / PM_RUN_INST_CMPL",
968 "MetricGroup": "general",
969 "MetricName": "l2_inst_miss_rate_percent"
970 },
971 {
972 "BriefDescription": "L2 dmand Load Miss Rate (per run instruction)(%)",
973 "MetricExpr": "PM_DATA_FROM_L2MISS * 100 / PM_RUN_INST_CMPL",
974 "MetricGroup": "general",
975 "MetricName": "l2_ld_miss_rate_percent"
976 },
977 {
978 "BriefDescription": "L2 PTEG Miss Rate (per run instruction)(%)",
979 "MetricExpr": "PM_DPTEG_FROM_L2MISS * 100 / PM_RUN_INST_CMPL",
980 "MetricGroup": "general",
981 "MetricName": "l2_pteg_miss_rate_percent"
982 },
983 {
984 "BriefDescription": "Percentage of L2 store misses per run instruction",
985 "MetricExpr": "PM_ST_MISS_L1 * 100 / PM_RUN_INST_CMPL",
986 "MetricGroup": "general",
987 "MetricName": "l2_st_miss_rate_percent"
988 },
989 {
990 "BriefDescription": "L3 Instruction Miss Rate (per instruction)(%)",
991 "MetricExpr": "PM_INST_FROM_L3MISS * 100 / PM_RUN_INST_CMPL",
992 "MetricGroup": "general",
993 "MetricName": "l3_inst_miss_rate_percent"
994 },
995 {
996 "BriefDescription": "L3 demand Load Miss Rate (per run instruction)(%)",
997 "MetricExpr": "PM_DATA_FROM_L3MISS * 100 / PM_RUN_INST_CMPL",
998 "MetricGroup": "general",
999 "MetricName": "l3_ld_miss_rate_percent"
1000 },
1001 {
1002 "BriefDescription": "L3 PTEG Miss Rate (per run instruction)(%)",
1003 "MetricExpr": "PM_DPTEG_FROM_L3MISS * 100 / PM_RUN_INST_CMPL",
1004 "MetricGroup": "general",
1005 "MetricName": "l3_pteg_miss_rate_percent"
1006 },
1007 {
1008 "BriefDescription": "Run cycles per cycle",
1009 "MetricExpr": "PM_RUN_CYC / PM_CYC*100",
1010 "MetricGroup": "general",
1011 "MetricName": "run_cycles_percent"
1012 },
1013 {
1014 "BriefDescription": "Percentage of cycles spent in SMT2 Mode",
1015 "MetricExpr": "(PM_RUN_CYC_SMT2_MODE/PM_RUN_CYC) * 100",
1016 "MetricGroup": "general",
1017 "MetricName": "smt2_cycles_percent"
1018 },
1019 {
1020 "BriefDescription": "Percentage of cycles spent in SMT4 Mode",
1021 "MetricExpr": "(PM_RUN_CYC_SMT4_MODE/PM_RUN_CYC) * 100",
1022 "MetricGroup": "general",
1023 "MetricName": "smt4_cycles_percent"
1024 },
1025 {
1026 "BriefDescription": "Percentage of cycles spent in SMT8 Mode",
1027 "MetricExpr": "(PM_RUN_CYC_SMT8_MODE/PM_RUN_CYC) * 100",
1028 "MetricGroup": "general",
1029 "MetricName": "smt8_cycles_percent"
1030 },
1031 {
1032 "BriefDescription": "IPC of all instructions completed by the core while this thread was stalled",
1033 "MetricExpr": "PM_CMPLU_STALL_OTHER_CMPL/PM_RUN_CYC",
1034 "MetricGroup": "general",
1035 "MetricName": "smt_benefit"
1036 },
1037 {
1038 "BriefDescription": "Instruction dispatch-to-completion ratio",
1039 "MetricExpr": "PM_INST_DISP / PM_INST_CMPL",
1040 "MetricGroup": "general",
1041 "MetricName": "speculation"
1042 },
1043 {
1044 "BriefDescription": "Percentage of cycles spent in Single Thread Mode",
1045 "MetricExpr": "(PM_RUN_CYC_ST_MODE/PM_RUN_CYC) * 100",
1046 "MetricGroup": "general",
1047 "MetricName": "st_cycles_percent"
1048 },
1049 {
1050 "BriefDescription": "% of ICache reloads from Distant L2 or L3 (Modified) per Inst",
1051 "MetricExpr": "PM_INST_FROM_DL2L3_MOD * 100 / PM_RUN_INST_CMPL",
1052 "MetricGroup": "instruction_misses_percent_per_inst",
1053 "MetricName": "inst_from_dl2l3_mod_rate_percent"
1054 },
1055 {
1056 "BriefDescription": "% of ICache reloads from Distant L2 or L3 (Shared) per Inst",
1057 "MetricExpr": "PM_INST_FROM_DL2L3_SHR * 100 / PM_RUN_INST_CMPL",
1058 "MetricGroup": "instruction_misses_percent_per_inst",
1059 "MetricName": "inst_from_dl2l3_shr_rate_percent"
1060 },
1061 {
1062 "BriefDescription": "% of ICache reloads from Distant L4 per Inst",
1063 "MetricExpr": "PM_INST_FROM_DL4 * 100 / PM_RUN_INST_CMPL",
1064 "MetricGroup": "instruction_misses_percent_per_inst",
1065 "MetricName": "inst_from_dl4_rate_percent"
1066 },
1067 {
1068 "BriefDescription": "% of ICache reloads from Distant Memory per Inst",
1069 "MetricExpr": "PM_INST_FROM_DMEM * 100 / PM_RUN_INST_CMPL",
1070 "MetricGroup": "instruction_misses_percent_per_inst",
1071 "MetricName": "inst_from_dmem_rate_percent"
1072 },
1073 {
1074 "BriefDescription": "% of ICache reloads from Private L2, other core per Inst",
1075 "MetricExpr": "PM_INST_FROM_L21_MOD * 100 / PM_RUN_INST_CMPL",
1076 "MetricGroup": "instruction_misses_percent_per_inst",
1077 "MetricName": "inst_from_l21_mod_rate_percent"
1078 },
1079 {
1080 "BriefDescription": "% of ICache reloads from Private L2, other core per Inst",
1081 "MetricExpr": "PM_INST_FROM_L21_SHR * 100 / PM_RUN_INST_CMPL",
1082 "MetricGroup": "instruction_misses_percent_per_inst",
1083 "MetricName": "inst_from_l21_shr_rate_percent"
1084 },
1085 {
1086 "BriefDescription": "% of ICache reloads from L2 per Inst",
1087 "MetricExpr": "PM_INST_FROM_L2 * 100 / PM_RUN_INST_CMPL",
1088 "MetricGroup": "instruction_misses_percent_per_inst",
1089 "MetricName": "inst_from_l2_rate_percent"
1090 },
1091 {
1092 "BriefDescription": "% of ICache reloads from Private L3, other core per Inst",
1093 "MetricExpr": "PM_INST_FROM_L31_MOD * 100 / PM_RUN_INST_CMPL",
1094 "MetricGroup": "instruction_misses_percent_per_inst",
1095 "MetricName": "inst_from_l31_mod_rate_percent"
1096 },
1097 {
1098 "BriefDescription": "% of ICache reloads from Private L3 other core per Inst",
1099 "MetricExpr": "PM_INST_FROM_L31_SHR * 100 / PM_RUN_INST_CMPL",
1100 "MetricGroup": "instruction_misses_percent_per_inst",
1101 "MetricName": "inst_from_l31_shr_rate_percent"
1102 },
1103 {
1104 "BriefDescription": "% of ICache reloads from L3 per Inst",
1105 "MetricExpr": "PM_INST_FROM_L3 * 100 / PM_RUN_INST_CMPL",
1106 "MetricGroup": "instruction_misses_percent_per_inst",
1107 "MetricName": "inst_from_l3_rate_percent"
1108 },
1109 {
1110 "BriefDescription": "% of ICache reloads from Local L4 per Inst",
1111 "MetricExpr": "PM_INST_FROM_LL4 * 100 / PM_RUN_INST_CMPL",
1112 "MetricGroup": "instruction_misses_percent_per_inst",
1113 "MetricName": "inst_from_ll4_rate_percent"
1114 },
1115 {
1116 "BriefDescription": "% of ICache reloads from Local Memory per Inst",
1117 "MetricExpr": "PM_INST_FROM_LMEM * 100 / PM_RUN_INST_CMPL",
1118 "MetricGroup": "instruction_misses_percent_per_inst",
1119 "MetricName": "inst_from_lmem_rate_percent"
1120 },
1121 {
1122 "BriefDescription": "% of ICache reloads from Remote L2 or L3 (Modified) per Inst",
1123 "MetricExpr": "PM_INST_FROM_RL2L3_MOD * 100 / PM_RUN_INST_CMPL",
1124 "MetricGroup": "instruction_misses_percent_per_inst",
1125 "MetricName": "inst_from_rl2l3_mod_rate_percent"
1126 },
1127 {
1128 "BriefDescription": "% of ICache reloads from Remote L2 or L3 (Shared) per Inst",
1129 "MetricExpr": "PM_INST_FROM_RL2L3_SHR * 100 / PM_RUN_INST_CMPL",
1130 "MetricGroup": "instruction_misses_percent_per_inst",
1131 "MetricName": "inst_from_rl2l3_shr_rate_percent"
1132 },
1133 {
1134 "BriefDescription": "% of ICache reloads from Remote L4 per Inst",
1135 "MetricExpr": "PM_INST_FROM_RL4 * 100 / PM_RUN_INST_CMPL",
1136 "MetricGroup": "instruction_misses_percent_per_inst",
1137 "MetricName": "inst_from_rl4_rate_percent"
1138 },
1139 {
1140 "BriefDescription": "% of ICache reloads from Remote Memory per Inst",
1141 "MetricExpr": "PM_INST_FROM_RMEM * 100 / PM_RUN_INST_CMPL",
1142 "MetricGroup": "instruction_misses_percent_per_inst",
1143 "MetricName": "inst_from_rmem_rate_percent"
1144 },
1145 {
1146 "BriefDescription": "Instruction Cache Miss Rate (Per run Instruction)(%)",
1147 "MetricExpr": "PM_L1_ICACHE_MISS * 100 / PM_RUN_INST_CMPL",
1148 "MetricGroup": "instruction_misses_percent_per_inst",
1149 "MetricName": "l1_inst_miss_rate_percent"
1150 },
1151 {
1152 "BriefDescription": "% Branches per instruction",
1153 "MetricExpr": "PM_BRU_FIN / PM_RUN_INST_CMPL",
1154 "MetricGroup": "instruction_mix",
1155 "MetricName": "branches_per_inst"
1156 },
1157 {
1158 "BriefDescription": "Total Fixed point operations",
1159 "MetricExpr": "(PM_FXU0_FIN + PM_FXU1_FIN)/PM_RUN_INST_CMPL",
1160 "MetricGroup": "instruction_mix",
1161 "MetricName": "fixed_per_inst"
1162 },
1163 {
1164 "BriefDescription": "FXU0 balance",
1165 "MetricExpr": "PM_FXU0_FIN / (PM_FXU0_FIN + PM_FXU1_FIN)",
1166 "MetricGroup": "instruction_mix",
1167 "MetricName": "fxu0_balance"
1168 },
1169 {
1170 "BriefDescription": "Fraction of cycles that FXU0 is in use",
1171 "MetricExpr": "PM_FXU0_FIN / PM_RUN_CYC",
1172 "MetricGroup": "instruction_mix",
1173 "MetricName": "fxu0_fin"
1174 },
1175 {
1176 "BriefDescription": "FXU0 only Busy",
1177 "MetricExpr": "PM_FXU0_BUSY_FXU1_IDLE / PM_CYC",
1178 "MetricGroup": "instruction_mix",
1179 "MetricName": "fxu0_only_busy"
1180 },
1181 {
1182 "BriefDescription": "Fraction of cycles that FXU1 is in use",
1183 "MetricExpr": "PM_FXU1_FIN / PM_RUN_CYC",
1184 "MetricGroup": "instruction_mix",
1185 "MetricName": "fxu1_fin"
1186 },
1187 {
1188 "BriefDescription": "FXU1 only Busy",
1189 "MetricExpr": "PM_FXU1_BUSY_FXU0_IDLE / PM_CYC",
1190 "MetricGroup": "instruction_mix",
1191 "MetricName": "fxu1_only_busy"
1192 },
1193 {
1194 "BriefDescription": "Both FXU Busy",
1195 "MetricExpr": "PM_FXU_BUSY / PM_CYC",
1196 "MetricGroup": "instruction_mix",
1197 "MetricName": "fxu_both_busy"
1198 },
1199 {
1200 "BriefDescription": "Both FXU Idle",
1201 "MetricExpr": "PM_FXU_IDLE / PM_CYC",
1202 "MetricGroup": "instruction_mix",
1203 "MetricName": "fxu_both_idle"
1204 },
1205 {
1206 "BriefDescription": "PCT instruction loads",
1207 "MetricExpr": "PM_LD_REF_L1 / PM_RUN_INST_CMPL",
1208 "MetricGroup": "instruction_mix",
1209 "MetricName": "loads_per_inst"
1210 },
1211 {
1212 "BriefDescription": "PCT instruction stores",
1213 "MetricExpr": "PM_ST_FIN / PM_RUN_INST_CMPL",
1214 "MetricGroup": "instruction_mix",
1215 "MetricName": "stores_per_inst"
1216 },
1217 {
1218 "BriefDescription": "Icache Fetchs per Icache Miss",
1219 "MetricExpr": "(PM_L1_ICACHE_MISS - PM_IC_PREF_WRITE) / PM_L1_ICACHE_MISS",
1220 "MetricGroup": "instruction_stats_percent_per_ref",
1221 "MetricName": "icache_miss_reload"
1222 },
1223 {
1224 "BriefDescription": "% of ICache reloads due to prefetch",
1225 "MetricExpr": "PM_IC_PREF_WRITE * 100 / PM_L1_ICACHE_MISS",
1226 "MetricGroup": "instruction_stats_percent_per_ref",
1227 "MetricName": "icache_pref_percent"
1228 },
1229 {
1230 "BriefDescription": "% of ICache reloads from Distant L2 or L3 (Modified)",
1231 "MetricExpr": "PM_INST_FROM_DL2L3_MOD * 100 / PM_L1_ICACHE_MISS",
1232 "MetricGroup": "instruction_stats_percent_per_ref",
1233 "MetricName": "inst_from_dl2l3_mod_percent"
1234 },
1235 {
1236 "BriefDescription": "% of ICache reloads from Distant L2 or L3 (Shared)",
1237 "MetricExpr": "PM_INST_FROM_DL2L3_SHR * 100 / PM_L1_ICACHE_MISS",
1238 "MetricGroup": "instruction_stats_percent_per_ref",
1239 "MetricName": "inst_from_dl2l3_shr_percent"
1240 },
1241 {
1242 "BriefDescription": "% of ICache reloads from Distant L4",
1243 "MetricExpr": "PM_INST_FROM_DL4 * 100 / PM_L1_ICACHE_MISS",
1244 "MetricGroup": "instruction_stats_percent_per_ref",
1245 "MetricName": "inst_from_dl4_percent"
1246 },
1247 {
1248 "BriefDescription": "% of ICache reloads from Distant Memory",
1249 "MetricExpr": "PM_INST_FROM_DMEM * 100 / PM_L1_ICACHE_MISS",
1250 "MetricGroup": "instruction_stats_percent_per_ref",
1251 "MetricName": "inst_from_dmem_percent"
1252 },
1253 {
1254 "BriefDescription": "% of ICache reloads from Private L2, other core",
1255 "MetricExpr": "PM_INST_FROM_L21_MOD * 100 / PM_L1_ICACHE_MISS",
1256 "MetricGroup": "instruction_stats_percent_per_ref",
1257 "MetricName": "inst_from_l21_mod_percent"
1258 },
1259 {
1260 "BriefDescription": "% of ICache reloads from Private L2, other core",
1261 "MetricExpr": "PM_INST_FROM_L21_SHR * 100 / PM_L1_ICACHE_MISS",
1262 "MetricGroup": "instruction_stats_percent_per_ref",
1263 "MetricName": "inst_from_l21_shr_percent"
1264 },
1265 {
1266 "BriefDescription": "% of ICache reloads from L2",
1267 "MetricExpr": "PM_INST_FROM_L2 * 100 / PM_L1_ICACHE_MISS",
1268 "MetricGroup": "instruction_stats_percent_per_ref",
1269 "MetricName": "inst_from_l2_percent"
1270 },
1271 {
1272 "BriefDescription": "% of ICache reloads from Private L3, other core",
1273 "MetricExpr": "PM_INST_FROM_L31_MOD * 100 / PM_L1_ICACHE_MISS",
1274 "MetricGroup": "instruction_stats_percent_per_ref",
1275 "MetricName": "inst_from_l31_mod_percent"
1276 },
1277 {
1278 "BriefDescription": "% of ICache reloads from Private L3, other core",
1279 "MetricExpr": "PM_INST_FROM_L31_SHR * 100 / PM_L1_ICACHE_MISS",
1280 "MetricGroup": "instruction_stats_percent_per_ref",
1281 "MetricName": "inst_from_l31_shr_percent"
1282 },
1283 {
1284 "BriefDescription": "% of ICache reloads from L3",
1285 "MetricExpr": "PM_INST_FROM_L3 * 100 / PM_L1_ICACHE_MISS",
1286 "MetricGroup": "instruction_stats_percent_per_ref",
1287 "MetricName": "inst_from_l3_percent"
1288 },
1289 {
1290 "BriefDescription": "% of ICache reloads from Local L4",
1291 "MetricExpr": "PM_INST_FROM_LL4 * 100 / PM_L1_ICACHE_MISS",
1292 "MetricGroup": "instruction_stats_percent_per_ref",
1293 "MetricName": "inst_from_ll4_percent"
1294 },
1295 {
1296 "BriefDescription": "% of ICache reloads from Local Memory",
1297 "MetricExpr": "PM_INST_FROM_LMEM * 100 / PM_L1_ICACHE_MISS",
1298 "MetricGroup": "instruction_stats_percent_per_ref",
1299 "MetricName": "inst_from_lmem_percent"
1300 },
1301 {
1302 "BriefDescription": "% of ICache reloads from Remote L2 or L3 (Modified)",
1303 "MetricExpr": "PM_INST_FROM_RL2L3_MOD * 100 / PM_L1_ICACHE_MISS",
1304 "MetricGroup": "instruction_stats_percent_per_ref",
1305 "MetricName": "inst_from_rl2l3_mod_percent"
1306 },
1307 {
1308 "BriefDescription": "% of ICache reloads from Remote L2 or L3 (Shared)",
1309 "MetricExpr": "PM_INST_FROM_RL2L3_SHR * 100 / PM_L1_ICACHE_MISS",
1310 "MetricGroup": "instruction_stats_percent_per_ref",
1311 "MetricName": "inst_from_rl2l3_shr_percent"
1312 },
1313 {
1314 "BriefDescription": "% of ICache reloads from Remote L4",
1315 "MetricExpr": "PM_INST_FROM_RL4 * 100 / PM_L1_ICACHE_MISS",
1316 "MetricGroup": "instruction_stats_percent_per_ref",
1317 "MetricName": "inst_from_rl4_percent"
1318 },
1319 {
1320 "BriefDescription": "% of ICache reloads from Remote Memory",
1321 "MetricExpr": "PM_INST_FROM_RMEM * 100 / PM_L1_ICACHE_MISS",
1322 "MetricGroup": "instruction_stats_percent_per_ref",
1323 "MetricName": "inst_from_rmem_percent"
1324 },
1325 {
1326 "BriefDescription": "Average number of stores that gather in the store buffer before being sent to an L2 RC machine",
1327 "MetricExpr": "PM_ST_CMPL / (PM_L2_ST / 2)",
1328 "MetricGroup": "l2_stats",
1329 "MetricName": "avg_stores_gathered"
1330 },
1331 {
1332 "BriefDescription": "L2 Store misses as a % of total L2 Store dispatches (per thread)",
1333 "MetricExpr": "PM_L2_ST_MISS / PM_L2_ST * 100",
1334 "MetricGroup": "l2_stats",
1335 "MetricName": "l2_st_miss_ratio_percent"
1336 },
1337 {
1338 "BriefDescription": "Percentage of L2 store misses per drained store. A drained store may contain multiple individual stores if they target the same line",
1339 "MetricExpr": "PM_L2_ST_MISS / (PM_L2_ST / 2)",
1340 "MetricGroup": "l2_stats",
1341 "MetricName": "l2_store_miss_ratio_percent"
1342 },
1343 {
1344 "BriefDescription": "average L1 miss latency using marked events",
1345 "MetricExpr": "PM_MRK_LD_MISS_L1_CYC / PM_MRK_LD_MISS_L1",
1346 "MetricGroup": "latency",
1347 "MetricName": "average_dl1miss_latency"
1348 },
1349 {
1350 "BriefDescription": "Average icache miss latency",
1351 "MetricExpr": "(PM_IC_DEMAND_CYC / PM_IC_DEMAND_REQ)",
1352 "MetricGroup": "latency",
1353 "MetricName": "average_il1_miss_latency"
1354 },
1355 {
1356 "BriefDescription": "average service time for SYNC",
1357 "MetricExpr": "PM_LSU_SRQ_SYNC_CYC / PM_LSU_SRQ_SYNC",
1358 "MetricGroup": "latency",
1359 "MetricName": "average_sync_cyc"
1360 },
1361 {
1362 "BriefDescription": "Cycles LMQ slot0 was active on an average",
1363 "MetricExpr": "PM_LSU_LMQ_S0_VALID / PM_LSU_LMQ_S0_ALLOC",
1364 "MetricGroup": "latency",
1365 "MetricName": "avg_lmq_life_time"
1366 },
1367 {
1368 "BriefDescription": "Average number of cycles LRQ stays active for one load. Slot 0 is VALID ONLY FOR EVEN THREADS",
1369 "MetricExpr": "PM_LSU_LRQ_S0_VALID / PM_LSU_LRQ_S0_ALLOC",
1370 "MetricGroup": "latency",
1371 "MetricName": "avg_lrq_life_time_even"
1372 },
1373 {
1374 "BriefDescription": "Average number of cycles LRQ stays active for one load. Slot 43 is valid ONLY FOR ODD THREADS",
1375 "MetricExpr": "PM_LSU_LRQ_S43_VALID / PM_LSU_LRQ_S43_ALLOC",
1376 "MetricGroup": "latency",
1377 "MetricName": "avg_lrq_life_time_odd"
1378 },
1379 {
1380 "BriefDescription": "Average number of cycles SRQ stays active for one load. Slot 0 is VALID ONLY FOR EVEN THREADS",
1381 "MetricExpr": "PM_LSU_SRQ_S0_VALID / PM_LSU_SRQ_S0_ALLOC",
1382 "MetricGroup": "latency",
1383 "MetricName": "avg_srq_life_time_even"
1384 },
1385 {
1386 "BriefDescription": "Average number of cycles SRQ stays active for one load. Slot 39 is valid ONLY FOR ODD THREADS",
1387 "MetricExpr": "PM_LSU_SRQ_S39_VALID / PM_LSU_SRQ_S39_ALLOC",
1388 "MetricGroup": "latency",
1389 "MetricName": "avg_srq_life_time_odd"
1390 },
1391 {
1392 "BriefDescription": "Marked background kill latency, measured in L2",
1393 "MetricExpr": "PM_MRK_FAB_RSP_BKILL_CYC / PM_MRK_FAB_RSP_BKILL",
1394 "MetricGroup": "latency",
1395 "MetricName": "bkill_latency"
1396 },
1397 {
1398 "BriefDescription": "Marked dclaim latency, measured in L2",
1399 "MetricExpr": "PM_MRK_FAB_RSP_DCLAIM_CYC / PM_MRK_FAB_RSP_DCLAIM",
1400 "MetricGroup": "latency",
1401 "MetricName": "dclaim_latency"
1402 },
1403 {
1404 "BriefDescription": "Marked L2L3 remote Load latency",
1405 "MetricExpr": "PM_MRK_DATA_FROM_DL2L3_MOD_CYC/ PM_MRK_DATA_FROM_DL2L3_MOD",
1406 "MetricGroup": "latency",
1407 "MetricName": "dl2l3_mod_latency"
1408 },
1409 {
1410 "BriefDescription": "Marked L2L3 distant Load latency",
1411 "MetricExpr": "PM_MRK_DATA_FROM_DL2L3_SHR_CYC/ PM_MRK_DATA_FROM_DL2L3_SHR",
1412 "MetricGroup": "latency",
1413 "MetricName": "dl2l3_shr_latency"
1414 },
1415 {
1416 "BriefDescription": "Distant L4 average load latency",
1417 "MetricExpr": "PM_MRK_DATA_FROM_DL4_CYC/ PM_MRK_DATA_FROM_DL4",
1418 "MetricGroup": "latency",
1419 "MetricName": "dl4_latency"
1420 },
1421 {
1422 "BriefDescription": "Marked Dmem Load latency",
1423 "MetricExpr": "PM_MRK_DATA_FROM_DMEM_CYC/ PM_MRK_DATA_FROM_DMEM",
1424 "MetricGroup": "latency",
1425 "MetricName": "dmem_latency"
1426 },
1427 {
1428 "BriefDescription": "estimated exposed miss latency for dL1 misses, ie load miss when we were NTC",
1429 "MetricExpr": "PM_MRK_LD_MISS_EXPOSED_CYC / PM_MRK_LD_MISS_EXPOSED",
1430 "MetricGroup": "latency",
1431 "MetricName": "exposed_dl1miss_latency"
1432 },
1433 {
1434 "BriefDescription": "Average load latency for all marked demand loads that came from L2.1 in the M state",
1435 "MetricExpr": "PM_MRK_DATA_FROM_L21_MOD_CYC/ PM_MRK_DATA_FROM_L21_MOD",
1436 "MetricGroup": "latency",
1437 "MetricName": "l21_mod_latency"
1438 },
1439 {
1440 "BriefDescription": "Average load latency for all marked demand loads that came from L2.1 in the S state",
1441 "MetricExpr": "PM_MRK_DATA_FROM_L21_SHR_CYC/ PM_MRK_DATA_FROM_L21_SHR",
1442 "MetricGroup": "latency",
1443 "MetricName": "l21_shr_latency"
1444 },
1445 {
1446 "BriefDescription": "Average load latency for all marked demand loads that came from the L2 and suffered a conflict at RC machine dispatch time due to load-hit-store",
1447 "MetricExpr": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC/ PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST",
1448 "MetricGroup": "latency",
1449 "MetricName": "l2_disp_conflict_ldhitst_latency"
1450 },
1451 {
1452 "BriefDescription": "Average load latency for all marked demand loads that came from the L2 and suffered a conflict at RC machine dispatch time NOT due load-hit-store",
1453 "MetricExpr": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC/ PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER",
1454 "MetricGroup": "latency",
1455 "MetricName": "l2_disp_conflict_other_latency"
1456 },
1457 {
1458 "BriefDescription": "Average load latency for all marked demand loads that came from the L2",
1459 "MetricExpr": "PM_MRK_DATA_FROM_L2_CYC/ PM_MRK_DATA_FROM_L2",
1460 "MetricGroup": "latency",
1461 "MetricName": "l2_latency"
1462 },
1463 {
1464 "BriefDescription": "Average load latency for all marked demand loads that were satisfied by lines prefetched into the L3. This information is forwarded from the L3",
1465 "MetricExpr": "PM_MRK_DATA_FROM_L2_MEPF_CYC/ PM_MRK_DATA_FROM_L2",
1466 "MetricGroup": "latency",
1467 "MetricName": "l2_mepf_latency"
1468 },
1469 {
1470 "BriefDescription": "Average load latency for all marked demand loads that came from the L2 and suffered no conflicts",
1471 "MetricExpr": "PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC/ PM_MRK_DATA_FROM_L2",
1472 "MetricGroup": "latency",
1473 "MetricName": "l2_no_conflict_latency"
1474 },
1475 {
1476 "BriefDescription": "Average load latency for all marked demand loads that came from the L3 and beyond",
1477 "MetricExpr": "PM_MRK_DATA_FROM_L2MISS_CYC/ PM_MRK_DATA_FROM_L2MISS",
1478 "MetricGroup": "latency",
1479 "MetricName": "l2miss_latency"
1480 },
1481 {
1482 "BriefDescription": "Marked L31 Load latency",
1483 "MetricExpr": "PM_MRK_DATA_FROM_L31_MOD_CYC/ PM_MRK_DATA_FROM_L31_MOD",
1484 "MetricGroup": "latency",
1485 "MetricName": "l31_mod_latency"
1486 },
1487 {
1488 "BriefDescription": "Marked L31 Load latency",
1489 "MetricExpr": "PM_MRK_DATA_FROM_L31_SHR_CYC/ PM_MRK_DATA_FROM_L31_SHR",
1490 "MetricGroup": "latency",
1491 "MetricName": "l31_shr_latency"
1492 },
1493 {
1494 "BriefDescription": "Average load latency for all marked demand loads that came from the L3",
1495 "MetricExpr": "PM_MRK_DATA_FROM_L3_CYC/ PM_MRK_DATA_FROM_L3",
1496 "MetricGroup": "latency",
1497 "MetricName": "l3_latency"
1498 },
1499 {
1500 "BriefDescription": "Average load latency for all marked demand loads that came from the L3 and suffered no conflicts",
1501 "MetricExpr": "PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC/ PM_MRK_DATA_FROM_L2",
1502 "MetricGroup": "latency",
1503 "MetricName": "l3_no_conflict_latency"
1504 },
1505 {
1506 "BriefDescription": "Average load latency for all marked demand loads that come from beyond the L3",
1507 "MetricExpr": "PM_MRK_DATA_FROM_L3MISS_CYC/ PM_MRK_DATA_FROM_L3MISS",
1508 "MetricGroup": "latency",
1509 "MetricName": "l3miss_latency"
1510 },
1511 {
1512 "BriefDescription": "Average latency for marked reloads that hit in the L3 on the MEPF state. i.e. lines that were prefetched into the L3",
1513 "MetricExpr": "PM_MRK_DATA_FROM_L3_MEPF_CYC/ PM_MRK_DATA_FROM_L3_MEPF",
1514 "MetricGroup": "latency",
1515 "MetricName": "l3pref_latency"
1516 },
1517 {
1518 "BriefDescription": "Local L4 average load latency",
1519 "MetricExpr": "PM_MRK_DATA_FROM_LL4_CYC/ PM_MRK_DATA_FROM_LL4",
1520 "MetricGroup": "latency",
1521 "MetricName": "ll4_latency"
1522 },
1523 {
1524 "BriefDescription": "Marked Lmem Load latency",
1525 "MetricExpr": "PM_MRK_DATA_FROM_LMEM_CYC/ PM_MRK_DATA_FROM_LMEM",
1526 "MetricGroup": "latency",
1527 "MetricName": "lmem_latency"
1528 },
1529 {
1530 "BriefDescription": "Latency for marked reloads that hit in the L2 or L3 of any other core on a different chip",
1531 "MetricExpr": "PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC/ PM_MRK_DATA_FROM_OFF_CHIP_CACHE",
1532 "MetricGroup": "latency",
1533 "MetricName": "off_chip_cache_latency"
1534 },
1535 {
1536 "BriefDescription": "Latency for marked reloads that hit in the L2 or L3 of any other core on the same chip",
1537 "MetricExpr": "PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC/ PM_MRK_DATA_FROM_ON_CHIP_CACHE",
1538 "MetricGroup": "latency",
1539 "MetricName": "on_chip_cache_latency"
1540 },
1541 {
1542 "BriefDescription": "Marked L2L3 remote Load latency",
1543 "MetricExpr": "PM_MRK_DATA_FROM_RL2L3_MOD_CYC/ PM_MRK_DATA_FROM_RL2L3_MOD",
1544 "MetricGroup": "latency",
1545 "MetricName": "rl2l3_mod_latency"
1546 },
1547 {
1548 "BriefDescription": "Marked L2L3 remote Load latency",
1549 "MetricExpr": "PM_MRK_DATA_FROM_RL2L3_SHR_CYC/ PM_MRK_DATA_FROM_RL2L3_SHR",
1550 "MetricGroup": "latency",
1551 "MetricName": "rl2l3_shr_latency"
1552 },
1553 {
1554 "BriefDescription": "Remote L4 average load latency",
1555 "MetricExpr": "PM_MRK_DATA_FROM_RL4_CYC/ PM_MRK_DATA_FROM_RL4",
1556 "MetricGroup": "latency",
1557 "MetricName": "rl4_latency"
1558 },
1559 {
1560 "BriefDescription": "Marked Rmem Load latency",
1561 "MetricExpr": "PM_MRK_DATA_FROM_RMEM_CYC/ PM_MRK_DATA_FROM_RMEM",
1562 "MetricGroup": "latency",
1563 "MetricName": "rmem_latency"
1564 },
1565 {
1566 "BriefDescription": "ERAT miss reject ratio",
1567 "MetricExpr": "PM_LSU_REJECT_ERAT_MISS * 100 / PM_RUN_INST_CMPL",
1568 "MetricGroup": "lsu_rejects",
1569 "MetricName": "erat_reject_rate_percent"
1570 },
1571 {
1572 "BriefDescription": "ERAT miss reject ratio",
1573 "MetricExpr": "PM_LSU_REJECT_ERAT_MISS * 100 / (PM_LSU_FIN - PM_LSU_FX_FIN)",
1574 "MetricGroup": "lsu_rejects",
1575 "MetricName": "erat_reject_ratio_percent"
1576 },
1577 {
1578 "BriefDescription": "LHS reject ratio",
1579 "MetricExpr": "PM_LSU_REJECT_LHS *100/ PM_RUN_INST_CMPL",
1580 "MetricGroup": "lsu_rejects",
1581 "MetricName": "lhs_reject_rate_percent"
1582 },
1583 {
1584 "BriefDescription": "LHS reject ratio",
1585 "MetricExpr": "PM_LSU_REJECT_LHS *100/ (PM_LSU_FIN - PM_LSU_FX_FIN)",
1586 "MetricGroup": "lsu_rejects",
1587 "MetricName": "lhs_reject_ratio_percent"
1588 },
1589 {
1590 "BriefDescription": "LMQ full reject ratio",
1591 "MetricExpr": "PM_LSU_REJECT_LMQ_FULL * 100 / PM_RUN_INST_CMPL",
1592 "MetricGroup": "lsu_rejects",
1593 "MetricName": "lmq_full_reject_rate_percent"
1594 },
1595 {
1596 "BriefDescription": "ERAT miss reject ratio",
1597 "MetricExpr": "PM_LSU_REJECT_LMQ_FULL * 100 / PM_LD_REF_L1",
1598 "MetricGroup": "lsu_rejects",
1599 "MetricName": "lmq_full_reject_ratio_percent"
1600 },
1601 {
1602 "BriefDescription": "LSU reject ratio",
1603 "MetricExpr": "PM_LSU_REJECT *100/ PM_RUN_INST_CMPL",
1604 "MetricGroup": "lsu_rejects",
1605 "MetricName": "lsu_reject_rate_percent"
1606 },
1607 {
1608 "BriefDescription": "LSU reject ratio",
1609 "MetricExpr": "PM_LSU_REJECT *100/ (PM_LSU_FIN - PM_LSU_FX_FIN)",
1610 "MetricGroup": "lsu_rejects",
1611 "MetricName": "lsu_reject_ratio_percent"
1612 },
1613 {
1614 "BriefDescription": "Ratio of reloads from local L4 to distant L4",
1615 "MetricExpr": "PM_DATA_FROM_LL4 / PM_DATA_FROM_DL4",
1616 "MetricGroup": "memory",
1617 "MetricName": "ld_ll4_per_ld_dmem"
1618 },
1619 {
1620 "BriefDescription": "Ratio of reloads from local L4 to remote+distant L4",
1621 "MetricExpr": "PM_DATA_FROM_LL4 / (PM_DATA_FROM_DL4 + PM_DATA_FROM_RL4)",
1622 "MetricGroup": "memory",
1623 "MetricName": "ld_ll4_per_ld_mem"
1624 },
1625 {
1626 "BriefDescription": "Ratio of reloads from local L4 to remote L4",
1627 "MetricExpr": "PM_DATA_FROM_LL4 / PM_DATA_FROM_RL4",
1628 "MetricGroup": "memory",
1629 "MetricName": "ld_ll4_per_ld_rl4"
1630 },
1631 {
1632 "BriefDescription": "Number of loads from local memory per loads from distant memory",
1633 "MetricExpr": "PM_DATA_FROM_LMEM / PM_DATA_FROM_DMEM",
1634 "MetricGroup": "memory",
1635 "MetricName": "ld_lmem_per_ld_dmem"
1636 },
1637 {
1638 "BriefDescription": "Number of loads from local memory per loads from remote and distant memory",
1639 "MetricExpr": "PM_DATA_FROM_LMEM / (PM_DATA_FROM_DMEM + PM_DATA_FROM_RMEM)",
1640 "MetricGroup": "memory",
1641 "MetricName": "ld_lmem_per_ld_mem"
1642 },
1643 {
1644 "BriefDescription": "Number of loads from local memory per loads from remote memory",
1645 "MetricExpr": "PM_DATA_FROM_LMEM / PM_DATA_FROM_RMEM",
1646 "MetricGroup": "memory",
1647 "MetricName": "ld_lmem_per_ld_rmem"
1648 },
1649 {
1650 "BriefDescription": "Number of loads from remote memory per loads from distant memory",
1651 "MetricExpr": "PM_DATA_FROM_RMEM / PM_DATA_FROM_DMEM",
1652 "MetricGroup": "memory",
1653 "MetricName": "ld_rmem_per_ld_dmem"
1654 },
1655 {
1656 "BriefDescription": "Memory locality",
1657 "MetricExpr": "(PM_DATA_FROM_LL4 + PM_DATA_FROM_LMEM) * 100/ (PM_DATA_FROM_LMEM + PM_DATA_FROM_LL4 + PM_DATA_FROM_RMEM + PM_DATA_FROM_RL4 + PM_DATA_FROM_DMEM + PM_DATA_FROM_DL4)",
1658 "MetricGroup": "memory",
1659 "MetricName": "mem_locality_percent"
1660 },
1661 {
1662 "BriefDescription": "DERAT Miss Rate (per run instruction)(%)",
1663 "MetricExpr": "PM_LSU_DERAT_MISS * 100 / PM_RUN_INST_CMPL",
1664 "MetricGroup": "pteg_reloads_percent_per_inst",
1665 "MetricName": "derat_miss_rate_percent"
1666 },
1667 {
1668 "BriefDescription": "% of DERAT reloads from Distant L2 or L3 (Modified) per inst",
1669 "MetricExpr": "PM_DPTEG_FROM_DL2L3_MOD * 100 / PM_RUN_INST_CMPL",
1670 "MetricGroup": "pteg_reloads_percent_per_inst",
1671 "MetricName": "pteg_from_dl2l3_mod_rate_percent"
1672 },
1673 {
1674 "BriefDescription": "% of DERAT reloads from Distant L2 or L3 (Shared) per inst",
1675 "MetricExpr": "PM_DPTEG_FROM_DL2L3_SHR * 100 / PM_RUN_INST_CMPL",
1676 "MetricGroup": "pteg_reloads_percent_per_inst",
1677 "MetricName": "pteg_from_dl2l3_shr_rate_percent"
1678 },
1679 {
1680 "BriefDescription": "% of DERAT reloads from Distant L4 per inst",
1681 "MetricExpr": "PM_DPTEG_FROM_DL4 * 100 / PM_RUN_INST_CMPL",
1682 "MetricGroup": "pteg_reloads_percent_per_inst",
1683 "MetricName": "pteg_from_dl4_rate_percent"
1684 },
1685 {
1686 "BriefDescription": "% of DERAT reloads from Distant Memory per inst",
1687 "MetricExpr": "PM_DPTEG_FROM_DMEM * 100 / PM_RUN_INST_CMPL",
1688 "MetricGroup": "pteg_reloads_percent_per_inst",
1689 "MetricName": "pteg_from_dmem_rate_percent"
1690 },
1691 {
1692 "BriefDescription": "% of DERAT reloads from Private L2, other core per inst",
1693 "MetricExpr": "PM_DPTEG_FROM_L21_MOD * 100 / PM_RUN_INST_CMPL",
1694 "MetricGroup": "pteg_reloads_percent_per_inst",
1695 "MetricName": "pteg_from_l21_mod_rate_percent"
1696 },
1697 {
1698 "BriefDescription": "% of DERAT reloads from Private L2, other core per inst",
1699 "MetricExpr": "PM_DPTEG_FROM_L21_SHR * 100 / PM_RUN_INST_CMPL",
1700 "MetricGroup": "pteg_reloads_percent_per_inst",
1701 "MetricName": "pteg_from_l21_shr_rate_percent"
1702 },
1703 {
1704 "BriefDescription": "% of DERAT reloads from L2 per inst",
1705 "MetricExpr": "PM_DPTEG_FROM_L2 * 100 / PM_RUN_INST_CMPL",
1706 "MetricGroup": "pteg_reloads_percent_per_inst",
1707 "MetricName": "pteg_from_l2_rate_percent"
1708 },
1709 {
1710 "BriefDescription": "% of DERAT reloads from Private L3, other core per inst",
1711 "MetricExpr": "PM_DPTEG_FROM_L31_MOD * 100 / PM_RUN_INST_CMPL",
1712 "MetricGroup": "pteg_reloads_percent_per_inst",
1713 "MetricName": "pteg_from_l31_mod_rate_percent"
1714 },
1715 {
1716 "BriefDescription": "% of DERAT reloads from Private L3, other core per inst",
1717 "MetricExpr": "PM_DPTEG_FROM_L31_SHR * 100 / PM_RUN_INST_CMPL",
1718 "MetricGroup": "pteg_reloads_percent_per_inst",
1719 "MetricName": "pteg_from_l31_shr_rate_percent"
1720 },
1721 {
1722 "BriefDescription": "% of DERAT reloads from L3 per inst",
1723 "MetricExpr": "PM_DPTEG_FROM_L3 * 100 / PM_RUN_INST_CMPL",
1724 "MetricGroup": "pteg_reloads_percent_per_inst",
1725 "MetricName": "pteg_from_l3_rate_percent"
1726 },
1727 {
1728 "BriefDescription": "% of DERAT reloads from Local L4 per inst",
1729 "MetricExpr": "PM_DPTEG_FROM_LL4 * 100 / PM_RUN_INST_CMPL",
1730 "MetricGroup": "pteg_reloads_percent_per_inst",
1731 "MetricName": "pteg_from_ll4_rate_percent"
1732 },
1733 {
1734 "BriefDescription": "% of DERAT reloads from Local Memory per inst",
1735 "MetricExpr": "PM_DPTEG_FROM_LMEM * 100 / PM_RUN_INST_CMPL",
1736 "MetricGroup": "pteg_reloads_percent_per_inst",
1737 "MetricName": "pteg_from_lmem_rate_percent"
1738 },
1739 {
1740 "BriefDescription": "% of DERAT reloads from Remote L2 or L3 (Modified) per inst",
1741 "MetricExpr": "PM_DPTEG_FROM_RL2L3_MOD * 100 / PM_RUN_INST_CMPL",
1742 "MetricGroup": "pteg_reloads_percent_per_inst",
1743 "MetricName": "pteg_from_rl2l3_mod_rate_percent"
1744 },
1745 {
1746 "BriefDescription": "% of DERAT reloads from Remote L2 or L3 (Shared) per inst",
1747 "MetricExpr": "PM_DPTEG_FROM_RL2L3_SHR * 100 / PM_RUN_INST_CMPL",
1748 "MetricGroup": "pteg_reloads_percent_per_inst",
1749 "MetricName": "pteg_from_rl2l3_shr_rate_percent"
1750 },
1751 {
1752 "BriefDescription": "% of DERAT reloads from Remote L4 per inst",
1753 "MetricExpr": "PM_DPTEG_FROM_RL4 * 100 / PM_RUN_INST_CMPL",
1754 "MetricGroup": "pteg_reloads_percent_per_inst",
1755 "MetricName": "pteg_from_rl4_rate_percent"
1756 },
1757 {
1758 "BriefDescription": "% of DERAT reloads from Remote Memory per inst",
1759 "MetricExpr": "PM_DPTEG_FROM_RMEM * 100 / PM_RUN_INST_CMPL",
1760 "MetricGroup": "pteg_reloads_percent_per_inst",
1761 "MetricName": "pteg_from_rmem_rate_percent"
1762 },
1763 {
1764 "BriefDescription": "% of DERAT misses that result in an ERAT reload",
1765 "MetricExpr": "PM_DTLB_MISS * 100 / PM_LSU_DERAT_MISS",
1766 "MetricGroup": "pteg_reloads_percent_per_ref",
1767 "MetricName": "derat_miss_reload_percent"
1768 },
1769 {
1770 "BriefDescription": "% of DERAT reloads from Distant L2 or L3 (Modified)",
1771 "MetricExpr": "PM_DPTEG_FROM_DL2L3_MOD * 100 / PM_DTLB_MISS",
1772 "MetricGroup": "pteg_reloads_percent_per_ref",
1773 "MetricName": "pteg_from_dl2l3_mod_percent"
1774 },
1775 {
1776 "BriefDescription": "% of DERAT reloads from Distant L2 or L3 (Shared)",
1777 "MetricExpr": "PM_DPTEG_FROM_DL2L3_SHR * 100 / PM_DTLB_MISS",
1778 "MetricGroup": "pteg_reloads_percent_per_ref",
1779 "MetricName": "pteg_from_dl2l3_shr_percent"
1780 },
1781 {
1782 "BriefDescription": "% of DERAT reloads from Distant L4",
1783 "MetricExpr": "PM_DPTEG_FROM_DL4 * 100 / PM_DTLB_MISS",
1784 "MetricGroup": "pteg_reloads_percent_per_ref",
1785 "MetricName": "pteg_from_dl4_percent"
1786 },
1787 {
1788 "BriefDescription": "% of DERAT reloads from Distant Memory",
1789 "MetricExpr": "PM_DPTEG_FROM_DMEM * 100 / PM_DTLB_MISS",
1790 "MetricGroup": "pteg_reloads_percent_per_ref",
1791 "MetricName": "pteg_from_dmem_percent"
1792 },
1793 {
1794 "BriefDescription": "% of DERAT reloads from Private L2, other core",
1795 "MetricExpr": "PM_DPTEG_FROM_L21_MOD * 100 / PM_DTLB_MISS",
1796 "MetricGroup": "pteg_reloads_percent_per_ref",
1797 "MetricName": "pteg_from_l21_mod_percent"
1798 },
1799 {
1800 "BriefDescription": "% of DERAT reloads from Private L2, other core",
1801 "MetricExpr": "PM_DPTEG_FROM_L21_SHR * 100 / PM_DTLB_MISS",
1802 "MetricGroup": "pteg_reloads_percent_per_ref",
1803 "MetricName": "pteg_from_l21_shr_percent"
1804 },
1805 {
1806 "BriefDescription": "% of DERAT reloads from L2",
1807 "MetricExpr": "PM_DPTEG_FROM_L2 * 100 / PM_DTLB_MISS",
1808 "MetricGroup": "pteg_reloads_percent_per_ref",
1809 "MetricName": "pteg_from_l2_percent"
1810 },
1811 {
1812 "BriefDescription": "% of DERAT reloads from Private L3, other core",
1813 "MetricExpr": "PM_DPTEG_FROM_L31_MOD * 100 / PM_DTLB_MISS",
1814 "MetricGroup": "pteg_reloads_percent_per_ref",
1815 "MetricName": "pteg_from_l31_mod_percent"
1816 },
1817 {
1818 "BriefDescription": "% of DERAT reloads from Private L3, other core",
1819 "MetricExpr": "PM_DPTEG_FROM_L31_SHR * 100 / PM_DTLB_MISS",
1820 "MetricGroup": "pteg_reloads_percent_per_ref",
1821 "MetricName": "pteg_from_l31_shr_percent"
1822 },
1823 {
1824 "BriefDescription": "% of DERAT reloads from L3",
1825 "MetricExpr": "PM_DPTEG_FROM_L3 * 100 / PM_DTLB_MISS",
1826 "MetricGroup": "pteg_reloads_percent_per_ref",
1827 "MetricName": "pteg_from_l3_percent"
1828 },
1829 {
1830 "BriefDescription": "% of DERAT reloads from Local L4",
1831 "MetricExpr": "PM_DPTEG_FROM_LL4 * 100 / PM_DTLB_MISS",
1832 "MetricGroup": "pteg_reloads_percent_per_ref",
1833 "MetricName": "pteg_from_ll4_percent"
1834 },
1835 {
1836 "BriefDescription": "% of DERAT reloads from Local Memory",
1837 "MetricExpr": "PM_DPTEG_FROM_LMEM * 100 / PM_DTLB_MISS",
1838 "MetricGroup": "pteg_reloads_percent_per_ref",
1839 "MetricName": "pteg_from_lmem_percent"
1840 },
1841 {
1842 "BriefDescription": "% of DERAT reloads from Remote L2 or L3 (Modified)",
1843 "MetricExpr": "PM_DPTEG_FROM_RL2L3_MOD * 100 / PM_DTLB_MISS",
1844 "MetricGroup": "pteg_reloads_percent_per_ref",
1845 "MetricName": "pteg_from_rl2l3_mod_percent"
1846 },
1847 {
1848 "BriefDescription": "% of DERAT reloads from Remote L2 or L3 (Shared)",
1849 "MetricExpr": "PM_DPTEG_FROM_RL2L3_SHR * 100 / PM_DTLB_MISS",
1850 "MetricGroup": "pteg_reloads_percent_per_ref",
1851 "MetricName": "pteg_from_rl2l3_shr_percent"
1852 },
1853 {
1854 "BriefDescription": "% of DERAT reloads from Remote L4",
1855 "MetricExpr": "PM_DPTEG_FROM_RL4 * 100 / PM_DTLB_MISS",
1856 "MetricGroup": "pteg_reloads_percent_per_ref",
1857 "MetricName": "pteg_from_rl4_percent"
1858 },
1859 {
1860 "BriefDescription": "% of DERAT reloads from Remote Memory",
1861 "MetricExpr": "PM_DPTEG_FROM_RMEM * 100 / PM_DTLB_MISS",
1862 "MetricGroup": "pteg_reloads_percent_per_ref",
1863 "MetricName": "pteg_from_rmem_percent"
1864 },
1865 {
1866 "BriefDescription": "% DERAT miss ratio for 16G page per inst",
1867 "MetricExpr": "100 * PM_DERAT_MISS_16G / PM_RUN_INST_CMPL",
1868 "MetricGroup": "translation",
1869 "MetricName": "derat_16g_miss_rate_percent"
1870 },
1871 {
1872 "BriefDescription": "DERAT miss ratio for 16G page",
1873 "MetricExpr": "PM_DERAT_MISS_16G / PM_LSU_DERAT_MISS",
1874 "MetricGroup": "translation",
1875 "MetricName": "derat_16g_miss_ratio"
1876 },
1877 {
1878 "BriefDescription": "% DERAT miss rate for 16M page per inst",
1879 "MetricExpr": "PM_DERAT_MISS_16M * 100 / PM_RUN_INST_CMPL",
1880 "MetricGroup": "translation",
1881 "MetricName": "derat_16m_miss_rate_percent"
1882 },
1883 {
1884 "BriefDescription": "DERAT miss ratio for 16M page",
1885 "MetricExpr": "PM_DERAT_MISS_16M / PM_LSU_DERAT_MISS",
1886 "MetricGroup": "translation",
1887 "MetricName": "derat_16m_miss_ratio"
1888 },
1889 {
1890 "BriefDescription": "% DERAT miss rate for 4K page per inst",
1891 "MetricExpr": "PM_DERAT_MISS_4K * 100 / PM_RUN_INST_CMPL",
1892 "MetricGroup": "translation",
1893 "MetricName": "derat_4k_miss_rate_percent"
1894 },
1895 {
1896 "BriefDescription": "DERAT miss ratio for 4K page",
1897 "MetricExpr": "PM_DERAT_MISS_4K / PM_LSU_DERAT_MISS",
1898 "MetricGroup": "translation",
1899 "MetricName": "derat_4k_miss_ratio"
1900 },
1901 {
1902 "BriefDescription": "% DERAT miss ratio for 64K page per inst",
1903 "MetricExpr": "PM_DERAT_MISS_64K * 100 / PM_RUN_INST_CMPL",
1904 "MetricGroup": "translation",
1905 "MetricName": "derat_64k_miss_rate_percent"
1906 },
1907 {
1908 "BriefDescription": "DERAT miss ratio for 64K page",
1909 "MetricExpr": "PM_DERAT_MISS_64K / PM_LSU_DERAT_MISS",
1910 "MetricGroup": "translation",
1911 "MetricName": "derat_64k_miss_ratio"
1912 },
1913 {
1914 "BriefDescription": "% DSLB_Miss_Rate per inst",
1915 "MetricExpr": "PM_DSLB_MISS * 100 / PM_RUN_INST_CMPL",
1916 "MetricGroup": "translation",
1917 "MetricName": "dslb_miss_rate_percent"
1918 },
1919 {
1920 "BriefDescription": "% ISLB miss rate per inst",
1921 "MetricExpr": "PM_ISLB_MISS * 100 / PM_RUN_INST_CMPL",
1922 "MetricGroup": "translation",
1923 "MetricName": "islb_miss_rate_percent"
1924 },
1925 {
1926 "BriefDescription": "Fraction of hits on any Centaur (local, remote, or distant) on either L4 or DRAM per L1 load ref",
1927 "MetricExpr": "PM_DATA_FROM_MEMORY / PM_LD_REF_L1",
1928 "MetricName": "any_centaur_ld_hit_ratio"
1929 },
1930 {
1931 "BriefDescription": "Base Completion Cycles",
1932 "MetricExpr": "PM_1PLUS_PPC_CMPL / PM_RUN_INST_CMPL",
1933 "MetricName": "base_completion_cpi"
1934 },
1935 {
1936 "BriefDescription": "Marked background kill latency, measured in L2",
1937 "MetricExpr": "PM_MRK_FAB_RSP_BKILL_CYC / PM_MRK_FAB_RSP_BKILL",
1938 "MetricName": "bkill_ratio_percent"
1939 },
1940 {
1941 "BriefDescription": "cycles",
1942 "MetricExpr": "PM_RUN_CYC",
1943 "MetricName": "custom_secs"
1944 },
1945 {
1946 "BriefDescription": "Fraction of hits on a distant chip's Centaur (L4 or DRAM) per L1 load ref",
1947 "MetricExpr": "(PM_DATA_FROM_DMEM + PM_DATA_FROM_DL4) / PM_LD_REF_L1",
1948 "MetricName": "distant_centaur_ld_hit_ratio"
1949 },
1950 {
1951 "BriefDescription": "% of DL1 reloads that came from the L3 and beyond",
1952 "MetricExpr": "PM_DATA_FROM_L2MISS * 100 / PM_L1_DCACHE_RELOAD_VALID",
1953 "MetricName": "dl1_reload_from_l2_miss_percent"
1954 },
1955 {
1956 "BriefDescription": "% of DL1 reloads from Private L3, other core per Inst",
1957 "MetricExpr": "(PM_DATA_FROM_L31_MOD + PM_DATA_FROM_L31_SHR) * 100 / PM_RUN_INST_CMPL",
1958 "MetricName": "dl1_reload_from_l31_rate_percent"
1959 },
1960 {
1961 "BriefDescription": "Percentage of DL1 reloads from L3 where the lines were brought into the L3 by a prefetch operation",
1962 "MetricExpr": "PM_DATA_FROM_L3_MEPF * 100 / PM_L1_DCACHE_RELOAD_VALID",
1963 "MetricName": "dl1_reload_from_l3_mepf_percent"
1964 },
1965 {
1966 "BriefDescription": "% of DL1 Reloads from beyond the local L3",
1967 "MetricExpr": "PM_DATA_FROM_L3MISS * 100 / PM_L1_DCACHE_RELOAD_VALID",
1968 "MetricName": "dl1_reload_from_l3_miss_percent"
1969 },
1970 {
1971 "BriefDescription": "Fraction of hits of a line in the M (exclusive) state on the L2 or L3 of a core on a distant chip per L1 load ref",
1972 "MetricExpr": "PM_DATA_FROM_DL2L3_MOD / PM_LD_REF_L1",
1973 "MetricName": "dl2l3_mod_ld_hit_ratio"
1974 },
1975 {
1976 "BriefDescription": "Fraction of hits of a line in the S state on the L2 or L3 of a core on a distant chip per L1 load ref",
1977 "MetricExpr": "PM_DATA_FROM_DL2L3_SHR / PM_LD_REF_L1",
1978 "MetricName": "dl2l3_shr_ld_hit_ratio"
1979 },
1980 {
1981 "BriefDescription": "Fraction of hits on a distant Centaur's cache per L1 load ref",
1982 "MetricExpr": "PM_DATA_FROM_DL4 / PM_LD_REF_L1",
1983 "MetricName": "dl4_ld_hit_ratio"
1984 },
1985 {
1986 "BriefDescription": "Fraction of hits on a distant Centaur's DRAM per L1 load ref",
1987 "MetricExpr": "PM_DATA_FROM_DMEM / PM_LD_REF_L1",
1988 "MetricName": "dmem_ld_hit_ratio"
1989 },
1990 {
1991 "BriefDescription": "Rate of DERAT reloads from L2",
1992 "MetricExpr": "PM_DPTEG_FROM_L2 * 100 / PM_RUN_INST_CMPL",
1993 "MetricName": "dpteg_from_l2_rate_percent"
1994 },
1995 {
1996 "BriefDescription": "Rate of DERAT reloads from L3",
1997 "MetricExpr": "PM_DPTEG_FROM_L3 * 100 / PM_RUN_INST_CMPL",
1998 "MetricName": "dpteg_from_l3_rate_percent"
1999 },
2000 {
2001 "BriefDescription": "Overhead of expansion cycles",
2002 "MetricExpr": "(PM_GRP_CMPL / PM_RUN_INST_CMPL) - (PM_1PLUS_PPC_CMPL / PM_RUN_INST_CMPL)",
2003 "MetricName": "expansion_overhead_cpi"
2004 },
2005 {
2006 "BriefDescription": "Total Fixed point operations executded in the Load/Store Unit following a load/store operation",
2007 "MetricExpr": "PM_LSU_FX_FIN/PM_RUN_INST_CMPL",
2008 "MetricName": "fixed_in_lsu_per_inst"
2009 },
2010 {
2011 "BriefDescription": "GCT empty cycles",
2012 "MetricExpr": "(PM_GCT_NOSLOT_CYC / PM_RUN_CYC) * 100",
2013 "MetricName": "gct_empty_percent"
2014 },
2015 {
2016 "BriefDescription": "Rate of IERAT reloads from L2",
2017 "MetricExpr": "PM_IPTEG_FROM_L2 * 100 / PM_RUN_INST_CMPL",
2018 "MetricName": "ipteg_from_l2_rate_percent"
2019 },
2020 {
2021 "BriefDescription": "Rate of IERAT reloads from L3",
2022 "MetricExpr": "PM_IPTEG_FROM_L3 * 100 / PM_RUN_INST_CMPL",
2023 "MetricName": "ipteg_from_l3_rate_percent"
2024 },
2025 {
2026 "BriefDescription": "Rate of IERAT reloads from local memory",
2027 "MetricExpr": "PM_IPTEG_FROM_LL4 * 100 / PM_RUN_INST_CMPL",
2028 "MetricName": "ipteg_from_ll4_rate_percent"
2029 },
2030 {
2031 "BriefDescription": "Rate of IERAT reloads from local memory",
2032 "MetricExpr": "PM_IPTEG_FROM_LMEM * 100 / PM_RUN_INST_CMPL",
2033 "MetricName": "ipteg_from_lmem_rate_percent"
2034 },
2035 {
2036 "BriefDescription": "Fraction of L1 hits per load ref",
2037 "MetricExpr": "(PM_LD_REF_L1 - PM_LD_MISS_L1) / PM_LD_REF_L1",
2038 "MetricName": "l1_ld_hit_ratio"
2039 },
2040 {
2041 "BriefDescription": "Fraction of L1 load misses per L1 load ref",
2042 "MetricExpr": "PM_LD_MISS_L1 / PM_LD_REF_L1",
2043 "MetricName": "l1_ld_miss_ratio"
2044 },
2045 {
2046 "BriefDescription": "Fraction of hits on another core's L2 on the same chip per L1 load ref",
2047 "MetricExpr": "(PM_DATA_FROM_L21_MOD + PM_DATA_FROM_L21_SHR) / PM_LD_REF_L1",
2048 "MetricName": "l2_1_ld_hit_ratio"
2049 },
2050 {
2051 "BriefDescription": "Fraction of hits of a line in the M (exclusive) state on another core's L2 on the same chip per L1 load ref",
2052 "MetricExpr": "PM_DATA_FROM_L21_MOD / PM_LD_REF_L1",
2053 "MetricName": "l2_1_mod_ld_hit_ratio"
2054 },
2055 {
2056 "BriefDescription": "Fraction of hits of a line in the S state on another core's L2 on the same chip per L1 load ref",
2057 "MetricExpr": "PM_DATA_FROM_L21_SHR / PM_LD_REF_L1",
2058 "MetricName": "l2_1_shr_ld_hit_ratio"
2059 },
2060 {
2061 "BriefDescription": "Average number of Castout machines used. 1 of 16 CO machines is sampled every L2 cycle",
2062 "MetricExpr": "(PM_CO_USAGE / PM_RUN_CYC) * 16",
2063 "MetricName": "l2_co_usage"
2064 },
2065 {
2066 "BriefDescription": "Fraction of L2 load hits per L1 load ref",
2067 "MetricExpr": "PM_DATA_FROM_L2 / PM_LD_REF_L1",
2068 "MetricName": "l2_ld_hit_ratio"
2069 },
2070 {
2071 "BriefDescription": "Fraction of L2 load misses per L1 load ref",
2072 "MetricExpr": "PM_DATA_FROM_L2MISS / PM_LD_REF_L1",
2073 "MetricName": "l2_ld_miss_ratio"
2074 },
2075 {
2076 "BriefDescription": "Fraction of L2 load hits per L1 load ref where the L2 experienced a Load-Hit-Store conflict",
2077 "MetricExpr": "PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST / PM_LD_REF_L1",
2078 "MetricName": "l2_lhs_ld_hit_ratio"
2079 },
2080 {
2081 "BriefDescription": "Fraction of L2 load hits per L1 load ref where the L2 did not experience a conflict",
2082 "MetricExpr": "PM_DATA_FROM_L2_NO_CONFLICT / PM_LD_REF_L1",
2083 "MetricName": "l2_no_conflict_ld_hit_ratio"
2084 },
2085 {
2086 "BriefDescription": "Fraction of L2 load hits per L1 load ref where the L2 experienced some conflict other than Load-Hit-Store",
2087 "MetricExpr": "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER / PM_LD_REF_L1",
2088 "MetricName": "l2_other_conflict_ld_hit_ratio"
2089 },
2090 {
2091 "BriefDescription": "Average number of Read/Claim machines used. 1 of 16 RC machines is sampled every L2 cycle",
2092 "MetricExpr": "(PM_RC_USAGE / PM_RUN_CYC) * 16",
2093 "MetricName": "l2_rc_usage"
2094 },
2095 {
2096 "BriefDescription": "Average number of Snoop machines used. 1 of 8 SN machines is sampled every L2 cycle",
2097 "MetricExpr": "(PM_SN_USAGE / PM_RUN_CYC) * 8",
2098 "MetricName": "l2_sn_usage"
2099 },
2100 {
2101 "BriefDescription": "Marked L31 Load latency",
2102 "MetricExpr": "(PM_MRK_DATA_FROM_L31_SHR_CYC + PM_MRK_DATA_FROM_L31_MOD_CYC) / (PM_MRK_DATA_FROM_L31_SHR + PM_MRK_DATA_FROM_L31_MOD)",
2103 "MetricName": "l31_latency"
2104 },
2105 {
2106 "BriefDescription": "Fraction of hits on another core's L3 on the same chip per L1 load ref",
2107 "MetricExpr": "(PM_DATA_FROM_L31_MOD + PM_DATA_FROM_L31_SHR) / PM_LD_REF_L1",
2108 "MetricName": "l3_1_ld_hit_ratio"
2109 },
2110 {
2111 "BriefDescription": "Fraction of hits of a line in the M (exclusive) state on another core's L3 on the same chip per L1 load ref",
2112 "MetricExpr": "PM_DATA_FROM_L31_MOD / PM_LD_REF_L1",
2113 "MetricName": "l3_1_mod_ld_hit_ratio"
2114 },
2115 {
2116 "BriefDescription": "Fraction of hits of a line in the S state on another core's L3 on the same chip per L1 load ref",
2117 "MetricExpr": "PM_DATA_FROM_L31_SHR / PM_LD_REF_L1",
2118 "MetricName": "l3_1_shr_ld_hit_ratio"
2119 },
2120 {
2121 "BriefDescription": "Fraction of L3 load hits per load ref where the demand load collided with a pending prefetch",
2122 "MetricExpr": "PM_DATA_FROM_L3_DISP_CONFLICT / PM_LD_REF_L1",
2123 "MetricName": "l3_conflict_ld_hit_ratio"
2124 },
2125 {
2126 "BriefDescription": "Fraction of L3 load hits per L1 load ref",
2127 "MetricExpr": "PM_DATA_FROM_L3 / PM_LD_REF_L1",
2128 "MetricName": "l3_ld_hit_ratio"
2129 },
2130 {
2131 "BriefDescription": "Fraction of L3 load misses per L1 load ref",
2132 "MetricExpr": "PM_DATA_FROM_L3MISS / PM_LD_REF_L1",
2133 "MetricName": "l3_ld_miss_ratio"
2134 },
2135 {
2136 "BriefDescription": "Fraction of L3 load hits per load ref where the L3 did not experience a conflict",
2137 "MetricExpr": "PM_DATA_FROM_L3_NO_CONFLICT / PM_LD_REF_L1",
2138 "MetricName": "l3_no_conflict_ld_hit_ratio"
2139 },
2140 {
2141 "BriefDescription": "Fraction of L3 hits on lines that were not in the MEPF state per L1 load ref",
2142 "MetricExpr": "(PM_DATA_FROM_L3 - PM_DATA_FROM_L3_MEPF) / PM_LD_REF_L1",
2143 "MetricName": "l3other_ld_hit_ratio"
2144 },
2145 {
2146 "BriefDescription": "Fraction of L3 hits on lines that were recently prefetched into the L3 (MEPF state) per L1 load ref",
2147 "MetricExpr": "PM_DATA_FROM_L3_MEPF / PM_LD_REF_L1",
2148 "MetricName": "l3pref_ld_hit_ratio"
2149 },
2150 {
2151 "BriefDescription": "Fraction of hits on a local Centaur's cache per L1 load ref",
2152 "MetricExpr": "PM_DATA_FROM_LL4 / PM_LD_REF_L1",
2153 "MetricName": "ll4_ld_hit_ratio"
2154 },
2155 {
2156 "BriefDescription": "Fraction of hits on a local Centaur's DRAM per L1 load ref",
2157 "MetricExpr": "PM_DATA_FROM_LMEM / PM_LD_REF_L1",
2158 "MetricName": "lmem_ld_hit_ratio"
2159 },
2160 {
2161 "BriefDescription": "Fraction of hits on a local Centaur (L4 or DRAM) per L1 load ref",
2162 "MetricExpr": "(PM_DATA_FROM_LMEM + PM_DATA_FROM_LL4) / PM_LD_REF_L1",
2163 "MetricName": "local_centaur_ld_hit_ratio"
2164 },
2165 {
2166 "BriefDescription": "Cycles stalled by Other LSU Operations",
2167 "MetricExpr": "(PM_CMPLU_STALL_LSU - PM_CMPLU_STALL_REJECT - PM_CMPLU_STALL_DCACHE_MISS - PM_CMPLU_STALL_STORE) / (PM_LD_REF_L1 - PM_LD_MISS_L1)",
2168 "MetricName": "lsu_stall_avg_cyc_per_l1hit_stfw"
2169 },
2170 {
2171 "BriefDescription": "Fraction of hits on another core's L2 or L3 on a different chip (remote or distant) per L1 load ref",
2172 "MetricExpr": "PM_DATA_FROM_OFF_CHIP_CACHE / PM_LD_REF_L1",
2173 "MetricName": "off_chip_cache_ld_hit_ratio"
2174 },
2175 {
2176 "BriefDescription": "Fraction of hits on another core's L2 or L3 on the same chip per L1 load ref",
2177 "MetricExpr": "PM_DATA_FROM_ON_CHIP_CACHE / PM_LD_REF_L1",
2178 "MetricName": "on_chip_cache_ld_hit_ratio"
2179 },
2180 {
2181 "BriefDescription": "Fraction of hits on a remote chip's Centaur (L4 or DRAM) per L1 load ref",
2182 "MetricExpr": "(PM_DATA_FROM_RMEM + PM_DATA_FROM_RL4) / PM_LD_REF_L1",
2183 "MetricName": "remote_centaur_ld_hit_ratio"
2184 },
2185 {
2186 "BriefDescription": "Percent of all FXU/VSU instructions that got rejected because of unavailable resources or facilities",
2187 "MetricExpr": "PM_ISU_REJECT_RES_NA *100/ PM_RUN_INST_CMPL",
2188 "MetricName": "resource_na_reject_rate_percent"
2189 },
2190 {
2191 "BriefDescription": "Fraction of hits of a line in the M (exclusive) state on the L2 or L3 of a core on a remote chip per L1 load ref",
2192 "MetricExpr": "PM_DATA_FROM_RL2L3_MOD / PM_LD_REF_L1",
2193 "MetricName": "rl2l3_mod_ld_hit_ratio"
2194 },
2195 {
2196 "BriefDescription": "Fraction of hits of a line in the S state on the L2 or L3 of a core on a remote chip per L1 load ref",
2197 "MetricExpr": "PM_DATA_FROM_RL2L3_SHR / PM_LD_REF_L1",
2198 "MetricName": "rl2l3_shr_ld_hit_ratio"
2199 },
2200 {
2201 "BriefDescription": "Fraction of hits on a remote Centaur's cache per L1 load ref",
2202 "MetricExpr": "PM_DATA_FROM_RL4 / PM_LD_REF_L1",
2203 "MetricName": "rl4_ld_hit_ratio"
2204 },
2205 {
2206 "BriefDescription": "Fraction of hits on a remote Centaur's DRAM per L1 load ref",
2207 "MetricExpr": "PM_DATA_FROM_RMEM / PM_LD_REF_L1",
2208 "MetricName": "rmem_ld_hit_ratio"
2209 },
2210 {
2211 "BriefDescription": "Percent of all FXU/VSU instructions that got rejected due to SAR Bypass",
2212 "MetricExpr": "PM_ISU_REJECT_SAR_BYPASS *100/ PM_RUN_INST_CMPL",
2213 "MetricName": "sar_bypass_reject_rate_percent"
2214 },
2215 {
2216 "BriefDescription": "Percent of all FXU/VSU instructions that got rejected because of unavailable sources",
2217 "MetricExpr": "PM_ISU_REJECT_SRC_NA *100/ PM_RUN_INST_CMPL",
2218 "MetricName": "source_na_reject_rate_percent"
2219 },
2220 {
2221 "BriefDescription": "Store forward rate",
2222 "MetricExpr": "100 * (PM_LSU0_SRQ_STFWD + PM_LSU1_SRQ_STFWD) / PM_RUN_INST_CMPL",
2223 "MetricName": "store_forward_rate_percent"
2224 },
2225 {
2226 "BriefDescription": "Store forward rate",
2227 "MetricExpr": "100 * (PM_LSU0_SRQ_STFWD + PM_LSU1_SRQ_STFWD) / (PM_LD_REF_L1 - PM_LD_MISS_L1)",
2228 "MetricName": "store_forward_ratio_percent"
2229 },
2230 {
2231 "BriefDescription": "Marked store latency, from core completion to L2 RC machine completion",
2232 "MetricExpr": "(PM_MRK_ST_L2DISP_TO_CMPL_CYC + PM_MRK_ST_DRAIN_TO_L2DISP_CYC) / PM_MRK_ST_NEST",
2233 "MetricName": "store_latency"
2234 },
2235 {
2236 "BriefDescription": "Cycles stalled by any sync",
2237 "MetricExpr": "(PM_CMPLU_STALL_LWSYNC + PM_CMPLU_STALL_HWSYNC) / PM_RUN_INST_CMPL",
2238 "MetricName": "sync_stall_cpi"
2239 },
2240 {
2241 "BriefDescription": "Percentage of lines that were prefetched into the L3 and evicted before they were consumed",
2242 "MetricExpr": "(PM_L3_CO_MEPF / 2) / PM_L3_PREF_ALL * 100",
2243 "MetricName": "wasted_l3_prefetch_percent"
2244 }
2245 ]
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