1 [
2 {
3 "Unit": "CPU-M-CF",
4 "EventCode": "128",
5 "EventName": "L1I_L2_SOURCED_WRITES",
6 "BriefDescription": "L1I L2 Sourced Writes",
7 "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from the Level-2 (L1.5) cache."
8 },
9 {
10 "Unit": "CPU-M-CF",
11 "EventCode": "129",
12 "EventName": "L1D_L2_SOURCED_WRITES",
13 "BriefDescription": "L1D L2 Sourced Writes",
14 "PublicDescription": "A directory write to the Level-1 Data Cache directory where the installed cache line was sourced from the Level-2 (L1.5) cache."
15 },
16 {
17 "Unit": "CPU-M-CF",
18 "EventCode": "130",
19 "EventName": "L1I_L3_LOCAL_WRITES",
20 "BriefDescription": "L1I L3 Local Writes",
21 "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the installed cache line was sourced from the Level-3 cache that is on the same book as the Instruction cache (Local L2 cache)."
22 },
23 {
24 "Unit": "CPU-M-CF",
25 "EventCode": "131",
26 "EventName": "L1D_L3_LOCAL_WRITES",
27 "BriefDescription": "L1D L3 Local Writes",
28 "PublicDescription": "A directory write to the Level-1 Data Cache directory where the installed cache line was source from the Level-3 cache that is on the same book as the Data cache (Local L2 cache)."
29 },
30 {
31 "Unit": "CPU-M-CF",
32 "EventCode": "132",
33 "EventName": "L1I_L3_REMOTE_WRITES",
34 "BriefDescription": "L1I L3 Remote Writes",
35 "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Instruction cache (Remote L2 cache)."
36 },
37 {
38 "Unit": "CPU-M-CF",
39 "EventCode": "133",
40 "EventName": "L1D_L3_REMOTE_WRITES",
41 "BriefDescription": "L1D L3 Remote Writes",
42 "PublicDescription": "A directory write to the Level-1 Data Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Data cache (Remote L2 cache)."
43 },
44 {
45 "Unit": "CPU-M-CF",
46 "EventCode": "134",
47 "EventName": "L1D_LMEM_SOURCED_WRITES",
48 "BriefDescription": "L1D Local Memory Sourced Writes",
49 "PublicDescription": "A directory write to the Level-1 Data Cache directory where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)."
50 },
51 {
52 "Unit": "CPU-M-CF",
53 "EventCode": "135",
54 "EventName": "L1I_LMEM_SOURCED_WRITES",
55 "BriefDescription": "L1I Local Memory Sourced Writes",
56 "PublicDescription": "A directory write to the Level-1 Instruction Cache where the installed cache line was sourced from memory that is attached to the s ame book as the Instruction cache (Local Memory)."
57 },
58 {
59 "Unit": "CPU-M-CF",
60 "EventCode": "136",
61 "EventName": "L1D_RO_EXCL_WRITES",
62 "BriefDescription": "L1D Read-only Exclusive Writes",
63 "PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
64 },
65 {
66 "Unit": "CPU-M-CF",
67 "EventCode": "137",
68 "EventName": "L1I_CACHELINE_INVALIDATES",
69 "BriefDescription": "L1I Cacheline Invalidates",
70 "PublicDescription": "A cache line in the Level-1 Instruction Cache has been invalidated by a store on the same CPU as the Level-1 Instruction Cache."
71 },
72 {
73 "Unit": "CPU-M-CF",
74 "EventCode": "138",
75 "EventName": "ITLB1_WRITES",
76 "BriefDescription": "ITLB1 Writes",
77 "PublicDescription": "A translation entry has been written into the Level-1 Instruction Translation Lookaside Buffer (ITLB1)."
78 },
79 {
80 "Unit": "CPU-M-CF",
81 "EventCode": "139",
82 "EventName": "DTLB1_WRITES",
83 "BriefDescription": "DTLB1 Writes",
84 "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer (DTLB1)."
85 },
86 {
87 "Unit": "CPU-M-CF",
88 "EventCode": "140",
89 "EventName": "TLB2_PTE_WRITES",
90 "BriefDescription": "TLB2 PTE Writes",
91 "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays."
92 },
93 {
94 "Unit": "CPU-M-CF",
95 "EventCode": "141",
96 "EventName": "TLB2_CRSTE_WRITES",
97 "BriefDescription": "TLB2 CRSTE Writes",
98 "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays."
99 },
100 {
101 "Unit": "CPU-M-CF",
102 "EventCode": "142",
103 "EventName": "TLB2_CRSTE_HPAGE_WRITES",
104 "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
105 "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation."
106 },
107 {
108 "Unit": "CPU-M-CF",
109 "EventCode": "145",
110 "EventName": "ITLB1_MISSES",
111 "BriefDescription": "ITLB1 Misses",
112 "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress."
113 },
114 {
115 "Unit": "CPU-M-CF",
116 "EventCode": "146",
117 "EventName": "DTLB1_MISSES",
118 "BriefDescription": "DTLB1 Misses",
119 "PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle an DTLB1 miss is in progress."
120 },
121 {
122 "Unit": "CPU-M-CF",
123 "EventCode": "147",
124 "EventName": "L2C_STORES_SENT",
125 "BriefDescription": "L2C Stores Sent",
126 "PublicDescription": "Incremented by one for every store sent to Level-2 (L1.5) cache."
127 }
128 ]
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