1 [
2 {
3 "BriefDescription": "L1D.HWPF_MISS",
4 "Counter": "0,1,2,3",
5 "EventCode": "0x51",
6 "EventName": "L1D.HWPF_MISS",
7 "SampleAfterValue": "1000003",
8 "UMask": "0x20",
9 "Unit": "cpu_core"
10 },
11 {
12 "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
13 "Counter": "0,1,2,3",
14 "EventCode": "0x51",
15 "EventName": "L1D.REPLACEMENT",
16 "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
17 "SampleAfterValue": "100003",
18 "UMask": "0x1",
19 "Unit": "cpu_core"
20 },
21 {
22 "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
23 "Counter": "0,1,2,3",
24 "EventCode": "0x48",
25 "EventName": "L1D_PEND_MISS.FB_FULL",
26 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
27 "SampleAfterValue": "1000003",
28 "UMask": "0x2",
29 "Unit": "cpu_core"
30 },
31 {
32 "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
33 "Counter": "0,1,2,3",
34 "CounterMask": "1",
35 "EdgeDetect": "1",
36 "EventCode": "0x48",
37 "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS",
38 "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
39 "SampleAfterValue": "1000003",
40 "UMask": "0x2",
41 "Unit": "cpu_core"
42 },
43 {
44 "BriefDescription": "This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS",
45 "Counter": "0,1,2,3",
46 "Deprecated": "1",
47 "EventCode": "0x48",
48 "EventName": "L1D_PEND_MISS.L2_STALL",
49 "SampleAfterValue": "1000003",
50 "UMask": "0x4",
51 "Unit": "cpu_core"
52 },
53 {
54 "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
55 "Counter": "0,1,2,3",
56 "EventCode": "0x48",
57 "EventName": "L1D_PEND_MISS.L2_STALLS",
58 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
59 "SampleAfterValue": "1000003",
60 "UMask": "0x4",
61 "Unit": "cpu_core"
62 },
63 {
64 "BriefDescription": "Number of L1D misses that are outstanding",
65 "Counter": "0,1,2,3",
66 "EventCode": "0x48",
67 "EventName": "L1D_PEND_MISS.PENDING",
68 "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
69 "SampleAfterValue": "1000003",
70 "UMask": "0x1",
71 "Unit": "cpu_core"
72 },
73 {
74 "BriefDescription": "Cycles with L1D load Misses outstanding.",
75 "Counter": "0,1,2,3",
76 "CounterMask": "1",
77 "EventCode": "0x48",
78 "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
79 "PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
80 "SampleAfterValue": "1000003",
81 "UMask": "0x1",
82 "Unit": "cpu_core"
83 },
84 {
85 "BriefDescription": "L2 cache lines filling L2",
86 "Counter": "0,1,2,3",
87 "EventCode": "0x25",
88 "EventName": "L2_LINES_IN.ALL",
89 "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
90 "SampleAfterValue": "100003",
91 "UMask": "0x1f",
92 "Unit": "cpu_core"
93 },
94 {
95 "BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses",
96 "Counter": "0,1,2,3",
97 "EventCode": "0x26",
98 "EventName": "L2_LINES_OUT.USELESS_HWPF",
99 "PublicDescription": "Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache",
100 "SampleAfterValue": "200003",
101 "UMask": "0x4",
102 "Unit": "cpu_core"
103 },
104 {
105 "BriefDescription": "All accesses to L2 cache [This event is alias to L2_RQSTS.REFERENCES]",
106 "Counter": "0,1,2,3",
107 "EventCode": "0x24",
108 "EventName": "L2_REQUEST.ALL",
109 "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES]",
110 "SampleAfterValue": "200003",
111 "UMask": "0xff",
112 "Unit": "cpu_core"
113 },
114 {
115 "BriefDescription": "Read requests with true-miss in L2 cache. [This event is alias to L2_RQSTS.MISS]",
116 "Counter": "0,1,2,3",
117 "EventCode": "0x24",
118 "EventName": "L2_REQUEST.MISS",
119 "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS]",
120 "SampleAfterValue": "200003",
121 "UMask": "0x3f",
122 "Unit": "cpu_core"
123 },
124 {
125 "BriefDescription": "L2 code requests",
126 "Counter": "0,1,2,3",
127 "EventCode": "0x24",
128 "EventName": "L2_RQSTS.ALL_CODE_RD",
129 "PublicDescription": "Counts the total number of L2 code requests.",
130 "SampleAfterValue": "200003",
131 "UMask": "0xe4",
132 "Unit": "cpu_core"
133 },
134 {
135 "BriefDescription": "Demand Data Read access L2 cache",
136 "Counter": "0,1,2,3",
137 "EventCode": "0x24",
138 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
139 "PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.",
140 "SampleAfterValue": "200003",
141 "UMask": "0xe1",
142 "Unit": "cpu_core"
143 },
144 {
145 "BriefDescription": "Demand requests that miss L2 cache",
146 "Counter": "0,1,2,3",
147 "EventCode": "0x24",
148 "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
149 "PublicDescription": "Counts demand requests that miss L2 cache.",
150 "SampleAfterValue": "200003",
151 "UMask": "0x27",
152 "Unit": "cpu_core"
153 },
154 {
155 "BriefDescription": "L2_RQSTS.ALL_HWPF",
156 "Counter": "0,1,2,3",
157 "EventCode": "0x24",
158 "EventName": "L2_RQSTS.ALL_HWPF",
159 "SampleAfterValue": "200003",
160 "UMask": "0xf0",
161 "Unit": "cpu_core"
162 },
163 {
164 "BriefDescription": "RFO requests to L2 cache.",
165 "Counter": "0,1,2,3",
166 "EventCode": "0x24",
167 "EventName": "L2_RQSTS.ALL_RFO",
168 "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
169 "SampleAfterValue": "200003",
170 "UMask": "0xe2",
171 "Unit": "cpu_core"
172 },
173 {
174 "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
175 "Counter": "0,1,2,3",
176 "EventCode": "0x24",
177 "EventName": "L2_RQSTS.CODE_RD_HIT",
178 "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
179 "SampleAfterValue": "200003",
180 "UMask": "0xc4",
181 "Unit": "cpu_core"
182 },
183 {
184 "BriefDescription": "L2 cache misses when fetching instructions",
185 "Counter": "0,1,2,3",
186 "EventCode": "0x24",
187 "EventName": "L2_RQSTS.CODE_RD_MISS",
188 "PublicDescription": "Counts L2 cache misses when fetching instructions.",
189 "SampleAfterValue": "200003",
190 "UMask": "0x24",
191 "Unit": "cpu_core"
192 },
193 {
194 "BriefDescription": "Demand Data Read requests that hit L2 cache",
195 "Counter": "0,1,2,3",
196 "EventCode": "0x24",
197 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
198 "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
199 "SampleAfterValue": "200003",
200 "UMask": "0xc1",
201 "Unit": "cpu_core"
202 },
203 {
204 "BriefDescription": "Demand Data Read miss L2 cache",
205 "Counter": "0,1,2,3",
206 "EventCode": "0x24",
207 "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
208 "PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once.",
209 "SampleAfterValue": "200003",
210 "UMask": "0x21",
211 "Unit": "cpu_core"
212 },
213 {
214 "BriefDescription": "L2_RQSTS.HWPF_MISS",
215 "Counter": "0,1,2,3",
216 "EventCode": "0x24",
217 "EventName": "L2_RQSTS.HWPF_MISS",
218 "SampleAfterValue": "200003",
219 "UMask": "0x30",
220 "Unit": "cpu_core"
221 },
222 {
223 "BriefDescription": "Read requests with true-miss in L2 cache. [This event is alias to L2_REQUEST.MISS]",
224 "Counter": "0,1,2,3",
225 "EventCode": "0x24",
226 "EventName": "L2_RQSTS.MISS",
227 "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS]",
228 "SampleAfterValue": "200003",
229 "UMask": "0x3f",
230 "Unit": "cpu_core"
231 },
232 {
233 "BriefDescription": "All accesses to L2 cache [This event is alias to L2_REQUEST.ALL]",
234 "Counter": "0,1,2,3",
235 "EventCode": "0x24",
236 "EventName": "L2_RQSTS.REFERENCES",
237 "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.ALL]",
238 "SampleAfterValue": "200003",
239 "UMask": "0xff",
240 "Unit": "cpu_core"
241 },
242 {
243 "BriefDescription": "RFO requests that hit L2 cache.",
244 "Counter": "0,1,2,3",
245 "EventCode": "0x24",
246 "EventName": "L2_RQSTS.RFO_HIT",
247 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
248 "SampleAfterValue": "200003",
249 "UMask": "0xc2",
250 "Unit": "cpu_core"
251 },
252 {
253 "BriefDescription": "RFO requests that miss L2 cache",
254 "Counter": "0,1,2,3",
255 "EventCode": "0x24",
256 "EventName": "L2_RQSTS.RFO_MISS",
257 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
258 "SampleAfterValue": "200003",
259 "UMask": "0x22",
260 "Unit": "cpu_core"
261 },
262 {
263 "BriefDescription": "SW prefetch requests that hit L2 cache.",
264 "Counter": "0,1,2,3",
265 "EventCode": "0x24",
266 "EventName": "L2_RQSTS.SWPF_HIT",
267 "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
268 "SampleAfterValue": "200003",
269 "UMask": "0xc8",
270 "Unit": "cpu_core"
271 },
272 {
273 "BriefDescription": "SW prefetch requests that miss L2 cache.",
274 "Counter": "0,1,2,3",
275 "EventCode": "0x24",
276 "EventName": "L2_RQSTS.SWPF_MISS",
277 "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
278 "SampleAfterValue": "200003",
279 "UMask": "0x28",
280 "Unit": "cpu_core"
281 },
282 {
283 "BriefDescription": "L2 writebacks that access L2 cache",
284 "Counter": "0,1,2,3",
285 "EventCode": "0x23",
286 "EventName": "L2_TRANS.L2_WB",
287 "PublicDescription": "Counts L2 writebacks that access L2 cache.",
288 "SampleAfterValue": "200003",
289 "UMask": "0x40",
290 "Unit": "cpu_core"
291 },
292 {
293 "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
294 "Counter": "0,1,2,3,4,5",
295 "EventCode": "0x2e",
296 "EventName": "LONGEST_LAT_CACHE.MISS",
297 "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
298 "SampleAfterValue": "200003",
299 "UMask": "0x41",
300 "Unit": "cpu_atom"
301 },
302 {
303 "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
304 "Counter": "0,1,2,3,4,5,6,7",
305 "EventCode": "0x2e",
306 "EventName": "LONGEST_LAT_CACHE.MISS",
307 "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
308 "SampleAfterValue": "100003",
309 "UMask": "0x41",
310 "Unit": "cpu_core"
311 },
312 {
313 "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
314 "Counter": "0,1,2,3,4,5",
315 "EventCode": "0x2e",
316 "EventName": "LONGEST_LAT_CACHE.REFERENCE",
317 "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
318 "SampleAfterValue": "200003",
319 "UMask": "0x4f",
320 "Unit": "cpu_atom"
321 },
322 {
323 "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
324 "Counter": "0,1,2,3,4,5,6,7",
325 "EventCode": "0x2e",
326 "EventName": "LONGEST_LAT_CACHE.REFERENCE",
327 "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
328 "SampleAfterValue": "100003",
329 "UMask": "0x4f",
330 "Unit": "cpu_core"
331 },
332 {
333 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
334 "Counter": "0,1,2,3,4,5",
335 "EventCode": "0x34",
336 "EventName": "MEM_BOUND_STALLS.IFETCH",
337 "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
338 "SampleAfterValue": "200003",
339 "UMask": "0x38",
340 "Unit": "cpu_atom"
341 },
342 {
343 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).",
344 "Counter": "0,1,2,3,4,5",
345 "EventCode": "0x34",
346 "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT",
347 "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM).",
348 "SampleAfterValue": "200003",
349 "UMask": "0x20",
350 "Unit": "cpu_atom"
351 },
352 {
353 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.",
354 "Counter": "0,1,2,3,4,5",
355 "EventCode": "0x34",
356 "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT",
357 "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.",
358 "SampleAfterValue": "200003",
359 "UMask": "0x8",
360 "Unit": "cpu_atom"
361 },
362 {
363 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.",
364 "Counter": "0,1,2,3,4,5",
365 "EventCode": "0x34",
366 "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT",
367 "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
368 "SampleAfterValue": "200003",
369 "UMask": "0x10",
370 "Unit": "cpu_atom"
371 },
372 {
373 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
374 "Counter": "0,1,2,3,4,5",
375 "EventCode": "0x34",
376 "EventName": "MEM_BOUND_STALLS.LOAD",
377 "SampleAfterValue": "200003",
378 "UMask": "0x7",
379 "Unit": "cpu_atom"
380 },
381 {
382 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
383 "Counter": "0,1,2,3,4,5",
384 "EventCode": "0x34",
385 "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT",
386 "SampleAfterValue": "200003",
387 "UMask": "0x4",
388 "Unit": "cpu_atom"
389 },
390 {
391 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.",
392 "Counter": "0,1,2,3,4,5",
393 "EventCode": "0x34",
394 "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT",
395 "SampleAfterValue": "200003",
396 "UMask": "0x1",
397 "Unit": "cpu_atom"
398 },
399 {
400 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.",
401 "Counter": "0,1,2,3,4,5",
402 "EventCode": "0x34",
403 "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT",
404 "PublicDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
405 "SampleAfterValue": "200003",
406 "UMask": "0x2",
407 "Unit": "cpu_atom"
408 },
409 {
410 "BriefDescription": "Retired load instructions.",
411 "Counter": "0,1,2,3",
412 "Data_LA": "1",
413 "EventCode": "0xd0",
414 "EventName": "MEM_INST_RETIRED.ALL_LOADS",
415 "PEBS": "1",
416 "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",
417 "SampleAfterValue": "1000003",
418 "UMask": "0x81",
419 "Unit": "cpu_core"
420 },
421 {
422 "BriefDescription": "Retired store instructions.",
423 "Counter": "0,1,2,3",
424 "Data_LA": "1",
425 "EventCode": "0xd0",
426 "EventName": "MEM_INST_RETIRED.ALL_STORES",
427 "PEBS": "1",
428 "PublicDescription": "Counts all retired store instructions.",
429 "SampleAfterValue": "1000003",
430 "UMask": "0x82",
431 "Unit": "cpu_core"
432 },
433 {
434 "BriefDescription": "All retired memory instructions.",
435 "Counter": "0,1,2,3",
436 "Data_LA": "1",
437 "EventCode": "0xd0",
438 "EventName": "MEM_INST_RETIRED.ANY",
439 "PEBS": "1",
440 "PublicDescription": "Counts all retired memory instructions - loads and stores.",
441 "SampleAfterValue": "1000003",
442 "UMask": "0x83",
443 "Unit": "cpu_core"
444 },
445 {
446 "BriefDescription": "Retired load instructions with locked access.",
447 "Counter": "0,1,2,3",
448 "Data_LA": "1",
449 "EventCode": "0xd0",
450 "EventName": "MEM_INST_RETIRED.LOCK_LOADS",
451 "PEBS": "1",
452 "PublicDescription": "Counts retired load instructions with locked access.",
453 "SampleAfterValue": "100007",
454 "UMask": "0x21",
455 "Unit": "cpu_core"
456 },
457 {
458 "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
459 "Counter": "0,1,2,3",
460 "Data_LA": "1",
461 "EventCode": "0xd0",
462 "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
463 "PEBS": "1",
464 "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",
465 "SampleAfterValue": "100003",
466 "UMask": "0x41",
467 "Unit": "cpu_core"
468 },
469 {
470 "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
471 "Counter": "0,1,2,3",
472 "Data_LA": "1",
473 "EventCode": "0xd0",
474 "EventName": "MEM_INST_RETIRED.SPLIT_STORES",
475 "PEBS": "1",
476 "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
477 "SampleAfterValue": "100003",
478 "UMask": "0x42",
479 "Unit": "cpu_core"
480 },
481 {
482 "BriefDescription": "Retired load instructions that miss the STLB.",
483 "Counter": "0,1,2,3",
484 "Data_LA": "1",
485 "EventCode": "0xd0",
486 "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
487 "PEBS": "1",
488 "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).",
489 "SampleAfterValue": "100003",
490 "UMask": "0x11",
491 "Unit": "cpu_core"
492 },
493 {
494 "BriefDescription": "Retired store instructions that miss the STLB.",
495 "Counter": "0,1,2,3",
496 "Data_LA": "1",
497 "EventCode": "0xd0",
498 "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
499 "PEBS": "1",
500 "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).",
501 "SampleAfterValue": "100003",
502 "UMask": "0x12",
503 "Unit": "cpu_core"
504 },
505 {
506 "BriefDescription": "Completed demand load uops that miss the L1 d-cache.",
507 "Counter": "0,1,2,3",
508 "EventCode": "0x43",
509 "EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY",
510 "PublicDescription": "Number of completed demand load requests that missed the L1 data cache including shadow misses (FB hits, merge to an ongoing L1D miss)",
511 "SampleAfterValue": "1000003",
512 "UMask": "0xfd",
513 "Unit": "cpu_core"
514 },
515 {
516 "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
517 "Counter": "0,1,2,3",
518 "Data_LA": "1",
519 "EventCode": "0xd2",
520 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
521 "PEBS": "1",
522 "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.",
523 "SampleAfterValue": "20011",
524 "UMask": "0x4",
525 "Unit": "cpu_core"
526 },
527 {
528 "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
529 "Counter": "0,1,2,3",
530 "Data_LA": "1",
531 "EventCode": "0xd2",
532 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
533 "PEBS": "1",
534 "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.",
535 "SampleAfterValue": "20011",
536 "UMask": "0x2",
537 "Unit": "cpu_core"
538 },
539 {
540 "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
541 "Counter": "0,1,2,3",
542 "Data_LA": "1",
543 "EventCode": "0xd2",
544 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
545 "PEBS": "1",
546 "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.",
547 "SampleAfterValue": "20011",
548 "UMask": "0x4",
549 "Unit": "cpu_core"
550 },
551 {
552 "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
553 "Counter": "0,1,2,3",
554 "Data_LA": "1",
555 "EventCode": "0xd2",
556 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
557 "PEBS": "1",
558 "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
559 "SampleAfterValue": "20011",
560 "UMask": "0x1",
561 "Unit": "cpu_core"
562 },
563 {
564 "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
565 "Counter": "0,1,2,3",
566 "Data_LA": "1",
567 "EventCode": "0xd2",
568 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
569 "PEBS": "1",
570 "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.",
571 "SampleAfterValue": "100003",
572 "UMask": "0x8",
573 "Unit": "cpu_core"
574 },
575 {
576 "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
577 "Counter": "0,1,2,3",
578 "Data_LA": "1",
579 "EventCode": "0xd2",
580 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
581 "PEBS": "1",
582 "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.",
583 "SampleAfterValue": "20011",
584 "UMask": "0x2",
585 "Unit": "cpu_core"
586 },
587 {
588 "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram",
589 "Counter": "0,1,2,3",
590 "Data_LA": "1",
591 "EventCode": "0xd3",
592 "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
593 "PEBS": "1",
594 "PublicDescription": "Retired load instructions which data sources missed L3 but serviced from local DRAM.",
595 "SampleAfterValue": "100007",
596 "UMask": "0x1",
597 "Unit": "cpu_core"
598 },
599 {
600 "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
601 "Counter": "0,1,2,3",
602 "Data_LA": "1",
603 "EventCode": "0xd4",
604 "EventName": "MEM_LOAD_MISC_RETIRED.UC",
605 "PEBS": "1",
606 "PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock).",
607 "SampleAfterValue": "100007",
608 "UMask": "0x4",
609 "Unit": "cpu_core"
610 },
611 {
612 "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
613 "Counter": "0,1,2,3",
614 "Data_LA": "1",
615 "EventCode": "0xd1",
616 "EventName": "MEM_LOAD_RETIRED.FB_HIT",
617 "PEBS": "1",
618 "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.",
619 "SampleAfterValue": "100007",
620 "UMask": "0x40",
621 "Unit": "cpu_core"
622 },
623 {
624 "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
625 "Counter": "0,1,2,3",
626 "Data_LA": "1",
627 "EventCode": "0xd1",
628 "EventName": "MEM_LOAD_RETIRED.L1_HIT",
629 "PEBS": "1",
630 "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.",
631 "SampleAfterValue": "1000003",
632 "UMask": "0x1",
633 "Unit": "cpu_core"
634 },
635 {
636 "BriefDescription": "Retired load instructions missed L1 cache as data sources",
637 "Counter": "0,1,2,3",
638 "Data_LA": "1",
639 "EventCode": "0xd1",
640 "EventName": "MEM_LOAD_RETIRED.L1_MISS",
641 "PEBS": "1",
642 "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
643 "SampleAfterValue": "200003",
644 "UMask": "0x8",
645 "Unit": "cpu_core"
646 },
647 {
648 "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
649 "Counter": "0,1,2,3",
650 "Data_LA": "1",
651 "EventCode": "0xd1",
652 "EventName": "MEM_LOAD_RETIRED.L2_HIT",
653 "PEBS": "1",
654 "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
655 "SampleAfterValue": "200003",
656 "UMask": "0x2",
657 "Unit": "cpu_core"
658 },
659 {
660 "BriefDescription": "Retired load instructions missed L2 cache as data sources",
661 "Counter": "0,1,2,3",
662 "Data_LA": "1",
663 "EventCode": "0xd1",
664 "EventName": "MEM_LOAD_RETIRED.L2_MISS",
665 "PEBS": "1",
666 "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
667 "SampleAfterValue": "100021",
668 "UMask": "0x10",
669 "Unit": "cpu_core"
670 },
671 {
672 "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
673 "Counter": "0,1,2,3",
674 "Data_LA": "1",
675 "EventCode": "0xd1",
676 "EventName": "MEM_LOAD_RETIRED.L3_HIT",
677 "PEBS": "1",
678 "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.",
679 "SampleAfterValue": "100021",
680 "UMask": "0x4",
681 "Unit": "cpu_core"
682 },
683 {
684 "BriefDescription": "Retired load instructions missed L3 cache as data sources",
685 "Counter": "0,1,2,3",
686 "Data_LA": "1",
687 "EventCode": "0xd1",
688 "EventName": "MEM_LOAD_RETIRED.L3_MISS",
689 "PEBS": "1",
690 "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.",
691 "SampleAfterValue": "50021",
692 "UMask": "0x20",
693 "Unit": "cpu_core"
694 },
695 {
696 "BriefDescription": "Counts the number of load uops retired that hit in DRAM.",
697 "Counter": "0,1,2,3,4,5",
698 "Data_LA": "1",
699 "EventCode": "0xd1",
700 "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
701 "PEBS": "1",
702 "SampleAfterValue": "200003",
703 "UMask": "0x80",
704 "Unit": "cpu_atom"
705 },
706 {
707 "BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.",
708 "Counter": "0,1,2,3,4,5",
709 "Data_LA": "1",
710 "EventCode": "0xd1",
711 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
712 "PEBS": "1",
713 "SampleAfterValue": "200003",
714 "UMask": "0x2",
715 "Unit": "cpu_atom"
716 },
717 {
718 "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.",
719 "Counter": "0,1,2,3,4,5",
720 "Data_LA": "1",
721 "EventCode": "0xd1",
722 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
723 "PEBS": "1",
724 "SampleAfterValue": "200003",
725 "UMask": "0x4",
726 "Unit": "cpu_atom"
727 },
728 {
729 "BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full.",
730 "Counter": "0,1,2,3,4,5",
731 "EventCode": "0x04",
732 "EventName": "MEM_SCHEDULER_BLOCK.ALL",
733 "SampleAfterValue": "20003",
734 "UMask": "0x7",
735 "Unit": "cpu_atom"
736 },
737 {
738 "BriefDescription": "Counts the number of cycles that uops are blocked due to a load buffer full condition.",
739 "Counter": "0,1,2,3,4,5",
740 "EventCode": "0x04",
741 "EventName": "MEM_SCHEDULER_BLOCK.LD_BUF",
742 "SampleAfterValue": "20003",
743 "UMask": "0x2",
744 "Unit": "cpu_atom"
745 },
746 {
747 "BriefDescription": "Counts the number of cycles that uops are blocked due to an RSV full condition.",
748 "Counter": "0,1,2,3,4,5",
749 "EventCode": "0x04",
750 "EventName": "MEM_SCHEDULER_BLOCK.RSV",
751 "SampleAfterValue": "20003",
752 "UMask": "0x4",
753 "Unit": "cpu_atom"
754 },
755 {
756 "BriefDescription": "Counts the number of cycles that uops are blocked due to a store buffer full condition.",
757 "Counter": "0,1,2,3,4,5",
758 "EventCode": "0x04",
759 "EventName": "MEM_SCHEDULER_BLOCK.ST_BUF",
760 "SampleAfterValue": "20003",
761 "UMask": "0x1",
762 "Unit": "cpu_atom"
763 },
764 {
765 "BriefDescription": "MEM_STORE_RETIRED.L2_HIT",
766 "Counter": "0,1,2,3",
767 "EventCode": "0x44",
768 "EventName": "MEM_STORE_RETIRED.L2_HIT",
769 "SampleAfterValue": "200003",
770 "UMask": "0x1",
771 "Unit": "cpu_core"
772 },
773 {
774 "BriefDescription": "Counts the number of load uops retired.",
775 "Counter": "0,1,2,3,4,5",
776 "Data_LA": "1",
777 "EventCode": "0xd0",
778 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
779 "PEBS": "1",
780 "PublicDescription": "Counts the total number of load uops retired.",
781 "SampleAfterValue": "200003",
782 "UMask": "0x81",
783 "Unit": "cpu_atom"
784 },
785 {
786 "BriefDescription": "Counts the number of store uops retired.",
787 "Counter": "0,1,2,3,4,5",
788 "Data_LA": "1",
789 "EventCode": "0xd0",
790 "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
791 "PEBS": "1",
792 "PublicDescription": "Counts the total number of store uops retired.",
793 "SampleAfterValue": "200003",
794 "UMask": "0x82",
795 "Unit": "cpu_atom"
796 },
797 {
798 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
799 "Counter": "0,1",
800 "Data_LA": "1",
801 "EventCode": "0xd0",
802 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
803 "MSRIndex": "0x3F6",
804 "MSRValue": "0x80",
805 "PEBS": "2",
806 "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
807 "SampleAfterValue": "1000003",
808 "UMask": "0x5",
809 "Unit": "cpu_atom"
810 },
811 {
812 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
813 "Counter": "0,1",
814 "Data_LA": "1",
815 "EventCode": "0xd0",
816 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
817 "MSRIndex": "0x3F6",
818 "MSRValue": "0x10",
819 "PEBS": "2",
820 "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
821 "SampleAfterValue": "1000003",
822 "UMask": "0x5",
823 "Unit": "cpu_atom"
824 },
825 {
826 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
827 "Counter": "0,1",
828 "Data_LA": "1",
829 "EventCode": "0xd0",
830 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
831 "MSRIndex": "0x3F6",
832 "MSRValue": "0x100",
833 "PEBS": "2",
834 "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
835 "SampleAfterValue": "1000003",
836 "UMask": "0x5",
837 "Unit": "cpu_atom"
838 },
839 {
840 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
841 "Counter": "0,1",
842 "Data_LA": "1",
843 "EventCode": "0xd0",
844 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
845 "MSRIndex": "0x3F6",
846 "MSRValue": "0x20",
847 "PEBS": "2",
848 "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
849 "SampleAfterValue": "1000003",
850 "UMask": "0x5",
851 "Unit": "cpu_atom"
852 },
853 {
854 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
855 "Counter": "0,1",
856 "Data_LA": "1",
857 "EventCode": "0xd0",
858 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
859 "MSRIndex": "0x3F6",
860 "MSRValue": "0x4",
861 "PEBS": "2",
862 "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
863 "SampleAfterValue": "1000003",
864 "UMask": "0x5",
865 "Unit": "cpu_atom"
866 },
867 {
868 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
869 "Counter": "0,1",
870 "Data_LA": "1",
871 "EventCode": "0xd0",
872 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
873 "MSRIndex": "0x3F6",
874 "MSRValue": "0x200",
875 "PEBS": "2",
876 "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
877 "SampleAfterValue": "1000003",
878 "UMask": "0x5",
879 "Unit": "cpu_atom"
880 },
881 {
882 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
883 "Counter": "0,1",
884 "Data_LA": "1",
885 "EventCode": "0xd0",
886 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
887 "MSRIndex": "0x3F6",
888 "MSRValue": "0x40",
889 "PEBS": "2",
890 "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
891 "SampleAfterValue": "1000003",
892 "UMask": "0x5",
893 "Unit": "cpu_atom"
894 },
895 {
896 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
897 "Counter": "0,1",
898 "Data_LA": "1",
899 "EventCode": "0xd0",
900 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
901 "MSRIndex": "0x3F6",
902 "MSRValue": "0x8",
903 "PEBS": "2",
904 "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
905 "SampleAfterValue": "1000003",
906 "UMask": "0x5",
907 "Unit": "cpu_atom"
908 },
909 {
910 "BriefDescription": "Counts the number of load uops retired that performed one or more locks.",
911 "Counter": "0,1,2,3,4,5",
912 "Data_LA": "1",
913 "EventCode": "0xd0",
914 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
915 "PEBS": "1",
916 "SampleAfterValue": "200003",
917 "UMask": "0x21",
918 "Unit": "cpu_atom"
919 },
920 {
921 "BriefDescription": "Counts the number of retired split load uops.",
922 "Counter": "0,1,2,3,4,5",
923 "Data_LA": "1",
924 "EventCode": "0xd0",
925 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
926 "PEBS": "1",
927 "SampleAfterValue": "200003",
928 "UMask": "0x41",
929 "Unit": "cpu_atom"
930 },
931 {
932 "BriefDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled.",
933 "Counter": "0,1,2,3,4,5",
934 "Data_LA": "1",
935 "EventCode": "0xd0",
936 "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
937 "PEBS": "2",
938 "PublicDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled. If PEBS is enabled and a PEBS record is generated, will populate PEBS Latency and PEBS Data Source fields accordingly.",
939 "SampleAfterValue": "1000003",
940 "UMask": "0x6",
941 "Unit": "cpu_atom"
942 },
943 {
944 "BriefDescription": "Retired memory uops for any access",
945 "Counter": "0,1,2,3,4,5,6,7",
946 "EventCode": "0xe5",
947 "EventName": "MEM_UOP_RETIRED.ANY",
948 "PublicDescription": "Number of retired micro-operations (uops) for load or store memory accesses",
949 "SampleAfterValue": "1000003",
950 "UMask": "0x3",
951 "Unit": "cpu_core"
952 },
953 {
954 "BriefDescription": "Counts demand data reads that were supplied by the L3 cache.",
955 "Counter": "0,1,2,3,4,5",
956 "EventCode": "0xB7",
957 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT",
958 "MSRIndex": "0x1a6,0x1a7",
959 "MSRValue": "0x3F803C0001",
960 "SampleAfterValue": "100003",
961 "UMask": "0x1",
962 "Unit": "cpu_atom"
963 },
964 {
965 "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
966 "Counter": "0,1,2,3,4,5",
967 "EventCode": "0xB7",
968 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
969 "MSRIndex": "0x1a6,0x1a7",
970 "MSRValue": "0x10003C0001",
971 "SampleAfterValue": "100003",
972 "UMask": "0x1",
973 "Unit": "cpu_atom"
974 },
975 {
976 "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.",
977 "Counter": "0,1,2,3",
978 "EventCode": "0x2A,0x2B",
979 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
980 "MSRIndex": "0x1a6,0x1a7",
981 "MSRValue": "0x10003C0001",
982 "SampleAfterValue": "100003",
983 "UMask": "0x1",
984 "Unit": "cpu_core"
985 },
986 {
987 "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
988 "Counter": "0,1,2,3,4,5",
989 "EventCode": "0xB7",
990 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
991 "MSRIndex": "0x1a6,0x1a7",
992 "MSRValue": "0x4003C0001",
993 "SampleAfterValue": "100003",
994 "UMask": "0x1",
995 "Unit": "cpu_atom"
996 },
997 {
998 "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
999 "Counter": "0,1,2,3,4,5",
1000 "EventCode": "0xB7",
1001 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
1002 "MSRIndex": "0x1a6,0x1a7",
1003 "MSRValue": "0x8003C0001",
1004 "SampleAfterValue": "100003",
1005 "UMask": "0x1",
1006 "Unit": "cpu_atom"
1007 },
1008 {
1009 "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches which forwarded the unmodified data to the requesting core.",
1010 "Counter": "0,1,2,3",
1011 "EventCode": "0x2A,0x2B",
1012 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
1013 "MSRIndex": "0x1a6,0x1a7",
1014 "MSRValue": "0x8003C0001",
1015 "SampleAfterValue": "100003",
1016 "UMask": "0x1",
1017 "Unit": "cpu_core"
1018 },
1019 {
1020 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.",
1021 "Counter": "0,1,2,3,4,5",
1022 "EventCode": "0xB7",
1023 "EventName": "OCR.DEMAND_RFO.L3_HIT",
1024 "MSRIndex": "0x1a6,0x1a7",
1025 "MSRValue": "0x3F803C0002",
1026 "SampleAfterValue": "100003",
1027 "UMask": "0x1",
1028 "Unit": "cpu_atom"
1029 },
1030 {
1031 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
1032 "Counter": "0,1,2,3,4,5",
1033 "EventCode": "0xB7",
1034 "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
1035 "MSRIndex": "0x1a6,0x1a7",
1036 "MSRValue": "0x10003C0002",
1037 "SampleAfterValue": "100003",
1038 "UMask": "0x1",
1039 "Unit": "cpu_atom"
1040 },
1041 {
1042 "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.",
1043 "Counter": "0,1,2,3",
1044 "EventCode": "0x2A,0x2B",
1045 "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
1046 "MSRIndex": "0x1a6,0x1a7",
1047 "MSRValue": "0x10003C0002",
1048 "SampleAfterValue": "100003",
1049 "UMask": "0x1",
1050 "Unit": "cpu_core"
1051 },
1052 {
1053 "BriefDescription": "OFFCORE_REQUESTS.ALL_REQUESTS",
1054 "Counter": "0,1,2,3",
1055 "EventCode": "0x21",
1056 "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
1057 "SampleAfterValue": "100003",
1058 "UMask": "0x80",
1059 "Unit": "cpu_core"
1060 },
1061 {
1062 "BriefDescription": "Demand and prefetch data reads",
1063 "Counter": "0,1,2,3",
1064 "EventCode": "0x21",
1065 "EventName": "OFFCORE_REQUESTS.DATA_RD",
1066 "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
1067 "SampleAfterValue": "100003",
1068 "UMask": "0x8",
1069 "Unit": "cpu_core"
1070 },
1071 {
1072 "BriefDescription": "Cacheable and noncacheable code read requests",
1073 "Counter": "0,1,2,3",
1074 "EventCode": "0x21",
1075 "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
1076 "PublicDescription": "Counts both cacheable and non-cacheable code read requests.",
1077 "SampleAfterValue": "100003",
1078 "UMask": "0x2",
1079 "Unit": "cpu_core"
1080 },
1081 {
1082 "BriefDescription": "Demand Data Read requests sent to uncore",
1083 "Counter": "0,1,2,3",
1084 "EventCode": "0x21",
1085 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
1086 "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
1087 "SampleAfterValue": "100003",
1088 "UMask": "0x1",
1089 "Unit": "cpu_core"
1090 },
1091 {
1092 "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
1093 "Counter": "0,1,2,3",
1094 "EventCode": "0x21",
1095 "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
1096 "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
1097 "SampleAfterValue": "100003",
1098 "UMask": "0x4",
1099 "Unit": "cpu_core"
1100 },
1101 {
1102 "BriefDescription": "This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
1103 "Counter": "0,1,2,3",
1104 "Deprecated": "1",
1105 "Errata": "ADL038",
1106 "EventCode": "0x20",
1107 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
1108 "SampleAfterValue": "1000003",
1109 "UMask": "0x8",
1110 "Unit": "cpu_core"
1111 },
1112 {
1113 "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
1114 "Counter": "0,1,2,3",
1115 "CounterMask": "1",
1116 "Errata": "ADL038",
1117 "EventCode": "0x20",
1118 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
1119 "SampleAfterValue": "1000003",
1120 "UMask": "0x8",
1121 "Unit": "cpu_core"
1122 },
1123 {
1124 "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",
1125 "Counter": "0,1,2,3",
1126 "CounterMask": "1",
1127 "EventCode": "0x20",
1128 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
1129 "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
1130 "SampleAfterValue": "1000003",
1131 "UMask": "0x2",
1132 "Unit": "cpu_core"
1133 },
1134 {
1135 "BriefDescription": "Cycles where at least 1 outstanding demand data read request is pending.",
1136 "Counter": "0,1,2,3",
1137 "CounterMask": "1",
1138 "EventCode": "0x20",
1139 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
1140 "SampleAfterValue": "2000003",
1141 "UMask": "0x1",
1142 "Unit": "cpu_core"
1143 },
1144 {
1145 "BriefDescription": "For every cycle where the core is waiting on at least 1 outstanding Demand RFO request, increments by 1.",
1146 "Counter": "0,1,2,3",
1147 "CounterMask": "1",
1148 "EventCode": "0x20",
1149 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
1150 "PublicDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
1151 "SampleAfterValue": "1000003",
1152 "UMask": "0x4",
1153 "Unit": "cpu_core"
1154 },
1155 {
1156 "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
1157 "Counter": "0,1,2,3",
1158 "Errata": "ADL038",
1159 "EventCode": "0x20",
1160 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
1161 "SampleAfterValue": "1000003",
1162 "UMask": "0x8",
1163 "Unit": "cpu_core"
1164 },
1165 {
1166 "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.",
1167 "Counter": "0,1,2,3",
1168 "EventCode": "0x20",
1169 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
1170 "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
1171 "SampleAfterValue": "1000003",
1172 "UMask": "0x2",
1173 "Unit": "cpu_core"
1174 },
1175 {
1176 "BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.",
1177 "Counter": "0,1,2,3",
1178 "EventCode": "0x20",
1179 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
1180 "PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
1181 "SampleAfterValue": "1000003",
1182 "UMask": "0x1",
1183 "Unit": "cpu_core"
1184 },
1185 {
1186 "BriefDescription": "Counts bus locks, accounts for cache line split locks and UC locks.",
1187 "Counter": "0,1,2,3",
1188 "EventCode": "0x2c",
1189 "EventName": "SQ_MISC.BUS_LOCK",
1190 "PublicDescription": "Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically. Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory.",
1191 "SampleAfterValue": "100003",
1192 "UMask": "0x10",
1193 "Unit": "cpu_core"
1194 },
1195 {
1196 "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.",
1197 "Counter": "0,1,2,3",
1198 "EventCode": "0x40",
1199 "EventName": "SW_PREFETCH_ACCESS.ANY",
1200 "SampleAfterValue": "100003",
1201 "UMask": "0xf",
1202 "Unit": "cpu_core"
1203 },
1204 {
1205 "BriefDescription": "Number of PREFETCHNTA instructions executed.",
1206 "Counter": "0,1,2,3",
1207 "EventCode": "0x40",
1208 "EventName": "SW_PREFETCH_ACCESS.NTA",
1209 "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
1210 "SampleAfterValue": "100003",
1211 "UMask": "0x1",
1212 "Unit": "cpu_core"
1213 },
1214 {
1215 "BriefDescription": "Number of PREFETCHW instructions executed.",
1216 "Counter": "0,1,2,3",
1217 "EventCode": "0x40",
1218 "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
1219 "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
1220 "SampleAfterValue": "100003",
1221 "UMask": "0x8",
1222 "Unit": "cpu_core"
1223 },
1224 {
1225 "BriefDescription": "Number of PREFETCHT0 instructions executed.",
1226 "Counter": "0,1,2,3",
1227 "EventCode": "0x40",
1228 "EventName": "SW_PREFETCH_ACCESS.T0",
1229 "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
1230 "SampleAfterValue": "100003",
1231 "UMask": "0x2",
1232 "Unit": "cpu_core"
1233 },
1234 {
1235 "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
1236 "Counter": "0,1,2,3",
1237 "EventCode": "0x40",
1238 "EventName": "SW_PREFETCH_ACCESS.T1_T2",
1239 "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
1240 "SampleAfterValue": "100003",
1241 "UMask": "0x4",
1242 "Unit": "cpu_core"
1243 },
1244 {
1245 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.",
1246 "Counter": "0,1,2,3,4,5",
1247 "EventCode": "0x71",
1248 "EventName": "TOPDOWN_FE_BOUND.ICACHE",
1249 "SampleAfterValue": "1000003",
1250 "UMask": "0x20",
1251 "Unit": "cpu_atom"
1252 }
1253 ]
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