1 [
2 {
3 "BriefDescription": "Number of times HLE abort was triggered",
4 "Counter": "0,1,2,3",
5 "EventCode": "0xc8",
6 "EventName": "HLE_RETIRED.ABORTED",
7 "PEBS": "1",
8 "PublicDescription": "Number of times HLE abort was triggered.",
9 "SampleAfterValue": "2000003",
10 "UMask": "0x4"
11 },
12 {
13 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
14 "Counter": "0,1,2,3",
15 "EventCode": "0xc8",
16 "EventName": "HLE_RETIRED.ABORTED_MISC1",
17 "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
18 "SampleAfterValue": "2000003",
19 "UMask": "0x8"
20 },
21 {
22 "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",
23 "Counter": "0,1,2,3",
24 "EventCode": "0xc8",
25 "EventName": "HLE_RETIRED.ABORTED_MISC2",
26 "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.",
27 "SampleAfterValue": "2000003",
28 "UMask": "0x10"
29 },
30 {
31 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
32 "Counter": "0,1,2,3",
33 "EventCode": "0xc8",
34 "EventName": "HLE_RETIRED.ABORTED_MISC3",
35 "PublicDescription": "Number of times a disallowed operation caused an HLE abort.",
36 "SampleAfterValue": "2000003",
37 "UMask": "0x20"
38 },
39 {
40 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
41 "Counter": "0,1,2,3",
42 "EventCode": "0xc8",
43 "EventName": "HLE_RETIRED.ABORTED_MISC4",
44 "PublicDescription": "Number of times HLE caused a fault.",
45 "SampleAfterValue": "2000003",
46 "UMask": "0x40"
47 },
48 {
49 "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
50 "Counter": "0,1,2,3",
51 "EventCode": "0xc8",
52 "EventName": "HLE_RETIRED.ABORTED_MISC5",
53 "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.",
54 "SampleAfterValue": "2000003",
55 "UMask": "0x80"
56 },
57 {
58 "BriefDescription": "Number of times HLE commit succeeded",
59 "Counter": "0,1,2,3",
60 "EventCode": "0xc8",
61 "EventName": "HLE_RETIRED.COMMIT",
62 "PublicDescription": "Number of times HLE commit succeeded.",
63 "SampleAfterValue": "2000003",
64 "UMask": "0x2"
65 },
66 {
67 "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",
68 "Counter": "0,1,2,3",
69 "EventCode": "0xc8",
70 "EventName": "HLE_RETIRED.START",
71 "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.",
72 "SampleAfterValue": "2000003",
73 "UMask": "0x1"
74 },
75 {
76 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
77 "Counter": "0,1,2,3",
78 "EventCode": "0xC3",
79 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
80 "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",
81 "SampleAfterValue": "100003",
82 "UMask": "0x2"
83 },
84 {
85 "BriefDescription": "Randomly selected loads with latency value being above 128",
86 "Counter": "3",
87 "Data_LA": "1",
88 "Errata": "BDM100, BDM35",
89 "EventCode": "0xcd",
90 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
91 "MSRIndex": "0x3F6",
92 "MSRValue": "0x80",
93 "PEBS": "2",
94 "PublicDescription": "Counts randomly selected loads with latency value being above 128.",
95 "SampleAfterValue": "1009",
96 "UMask": "0x1"
97 },
98 {
99 "BriefDescription": "Randomly selected loads with latency value being above 16",
100 "Counter": "3",
101 "Data_LA": "1",
102 "Errata": "BDM100, BDM35",
103 "EventCode": "0xcd",
104 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
105 "MSRIndex": "0x3F6",
106 "MSRValue": "0x10",
107 "PEBS": "2",
108 "PublicDescription": "Counts randomly selected loads with latency value being above 16.",
109 "SampleAfterValue": "20011",
110 "UMask": "0x1"
111 },
112 {
113 "BriefDescription": "Randomly selected loads with latency value being above 256",
114 "Counter": "3",
115 "Data_LA": "1",
116 "Errata": "BDM100, BDM35",
117 "EventCode": "0xcd",
118 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
119 "MSRIndex": "0x3F6",
120 "MSRValue": "0x100",
121 "PEBS": "2",
122 "PublicDescription": "Counts randomly selected loads with latency value being above 256.",
123 "SampleAfterValue": "503",
124 "UMask": "0x1"
125 },
126 {
127 "BriefDescription": "Randomly selected loads with latency value being above 32",
128 "Counter": "3",
129 "Data_LA": "1",
130 "Errata": "BDM100, BDM35",
131 "EventCode": "0xcd",
132 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
133 "MSRIndex": "0x3F6",
134 "MSRValue": "0x20",
135 "PEBS": "2",
136 "PublicDescription": "Counts randomly selected loads with latency value being above 32.",
137 "SampleAfterValue": "100007",
138 "UMask": "0x1"
139 },
140 {
141 "BriefDescription": "Randomly selected loads with latency value being above 4",
142 "Counter": "3",
143 "Data_LA": "1",
144 "Errata": "BDM100, BDM35",
145 "EventCode": "0xcd",
146 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
147 "MSRIndex": "0x3F6",
148 "MSRValue": "0x4",
149 "PEBS": "2",
150 "PublicDescription": "Counts randomly selected loads with latency value being above four.",
151 "SampleAfterValue": "100003",
152 "UMask": "0x1"
153 },
154 {
155 "BriefDescription": "Randomly selected loads with latency value being above 512",
156 "Counter": "3",
157 "Data_LA": "1",
158 "Errata": "BDM100, BDM35",
159 "EventCode": "0xcd",
160 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
161 "MSRIndex": "0x3F6",
162 "MSRValue": "0x200",
163 "PEBS": "2",
164 "PublicDescription": "Counts randomly selected loads with latency value being above 512.",
165 "SampleAfterValue": "101",
166 "UMask": "0x1"
167 },
168 {
169 "BriefDescription": "Randomly selected loads with latency value being above 64",
170 "Counter": "3",
171 "Data_LA": "1",
172 "Errata": "BDM100, BDM35",
173 "EventCode": "0xcd",
174 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
175 "MSRIndex": "0x3F6",
176 "MSRValue": "0x40",
177 "PEBS": "2",
178 "PublicDescription": "Counts randomly selected loads with latency value being above 64.",
179 "SampleAfterValue": "2003",
180 "UMask": "0x1"
181 },
182 {
183 "BriefDescription": "Randomly selected loads with latency value being above 8",
184 "Counter": "3",
185 "Data_LA": "1",
186 "Errata": "BDM100, BDM35",
187 "EventCode": "0xcd",
188 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
189 "MSRIndex": "0x3F6",
190 "MSRValue": "0x8",
191 "PEBS": "2",
192 "PublicDescription": "Counts randomly selected loads with latency value being above eight.",
193 "SampleAfterValue": "50021",
194 "UMask": "0x1"
195 },
196 {
197 "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
198 "Counter": "0,1,2,3",
199 "EventCode": "0x05",
200 "EventName": "MISALIGN_MEM_REF.LOADS",
201 "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",
202 "SampleAfterValue": "2000003",
203 "UMask": "0x1"
204 },
205 {
206 "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
207 "Counter": "0,1,2,3",
208 "EventCode": "0x05",
209 "EventName": "MISALIGN_MEM_REF.STORES",
210 "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",
211 "SampleAfterValue": "2000003",
212 "UMask": "0x2"
213 },
214 {
215 "BriefDescription": "Number of times RTM abort was triggered",
216 "Counter": "0,1,2,3",
217 "EventCode": "0xc9",
218 "EventName": "RTM_RETIRED.ABORTED",
219 "PEBS": "1",
220 "PublicDescription": "Number of times RTM abort was triggered .",
221 "SampleAfterValue": "2000003",
222 "UMask": "0x4"
223 },
224 {
225 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
226 "Counter": "0,1,2,3",
227 "EventCode": "0xc9",
228 "EventName": "RTM_RETIRED.ABORTED_MISC1",
229 "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
230 "SampleAfterValue": "2000003",
231 "UMask": "0x8"
232 },
233 {
234 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
235 "Counter": "0,1,2,3",
236 "EventCode": "0xc9",
237 "EventName": "RTM_RETIRED.ABORTED_MISC2",
238 "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.",
239 "SampleAfterValue": "2000003",
240 "UMask": "0x10"
241 },
242 {
243 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
244 "Counter": "0,1,2,3",
245 "EventCode": "0xc9",
246 "EventName": "RTM_RETIRED.ABORTED_MISC3",
247 "PublicDescription": "Number of times a disallowed operation caused an RTM abort.",
248 "SampleAfterValue": "2000003",
249 "UMask": "0x20"
250 },
251 {
252 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
253 "Counter": "0,1,2,3",
254 "EventCode": "0xc9",
255 "EventName": "RTM_RETIRED.ABORTED_MISC4",
256 "PublicDescription": "Number of times a RTM caused a fault.",
257 "SampleAfterValue": "2000003",
258 "UMask": "0x40"
259 },
260 {
261 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
262 "Counter": "0,1,2,3",
263 "EventCode": "0xc9",
264 "EventName": "RTM_RETIRED.ABORTED_MISC5",
265 "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.",
266 "SampleAfterValue": "2000003",
267 "UMask": "0x80"
268 },
269 {
270 "BriefDescription": "Number of times RTM commit succeeded",
271 "Counter": "0,1,2,3",
272 "EventCode": "0xc9",
273 "EventName": "RTM_RETIRED.COMMIT",
274 "PublicDescription": "Number of times RTM commit succeeded.",
275 "SampleAfterValue": "2000003",
276 "UMask": "0x2"
277 },
278 {
279 "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
280 "Counter": "0,1,2,3",
281 "EventCode": "0xc9",
282 "EventName": "RTM_RETIRED.START",
283 "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.",
284 "SampleAfterValue": "2000003",
285 "UMask": "0x1"
286 },
287 {
288 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
289 "Counter": "0,1,2,3",
290 "EventCode": "0x5d",
291 "EventName": "TX_EXEC.MISC1",
292 "SampleAfterValue": "2000003",
293 "UMask": "0x1"
294 },
295 {
296 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
297 "Counter": "0,1,2,3",
298 "EventCode": "0x5d",
299 "EventName": "TX_EXEC.MISC2",
300 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
301 "SampleAfterValue": "2000003",
302 "UMask": "0x2"
303 },
304 {
305 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
306 "Counter": "0,1,2,3",
307 "EventCode": "0x5d",
308 "EventName": "TX_EXEC.MISC3",
309 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
310 "SampleAfterValue": "2000003",
311 "UMask": "0x4"
312 },
313 {
314 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
315 "Counter": "0,1,2,3",
316 "EventCode": "0x5d",
317 "EventName": "TX_EXEC.MISC4",
318 "PublicDescription": "RTM region detected inside HLE.",
319 "SampleAfterValue": "2000003",
320 "UMask": "0x8"
321 },
322 {
323 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
324 "Counter": "0,1,2,3",
325 "EventCode": "0x5d",
326 "EventName": "TX_EXEC.MISC5",
327 "SampleAfterValue": "2000003",
328 "UMask": "0x10"
329 },
330 {
331 "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
332 "Counter": "0,1,2,3",
333 "EventCode": "0x54",
334 "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
335 "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.",
336 "SampleAfterValue": "2000003",
337 "UMask": "0x2"
338 },
339 {
340 "BriefDescription": "Number of times a TSX line had a cache conflict",
341 "Counter": "0,1,2,3",
342 "EventCode": "0x54",
343 "EventName": "TX_MEM.ABORT_CONFLICT",
344 "PublicDescription": "Number of times a TSX line had a cache conflict.",
345 "SampleAfterValue": "2000003",
346 "UMask": "0x1"
347 },
348 {
349 "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
350 "Counter": "0,1,2,3",
351 "EventCode": "0x54",
352 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
353 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
354 "SampleAfterValue": "2000003",
355 "UMask": "0x10"
356 },
357 {
358 "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
359 "Counter": "0,1,2,3",
360 "EventCode": "0x54",
361 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
362 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
363 "SampleAfterValue": "2000003",
364 "UMask": "0x8"
365 },
366 {
367 "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
368 "Counter": "0,1,2,3",
369 "EventCode": "0x54",
370 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
371 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
372 "SampleAfterValue": "2000003",
373 "UMask": "0x20"
374 },
375 {
376 "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
377 "Counter": "0,1,2,3",
378 "EventCode": "0x54",
379 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
380 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
381 "SampleAfterValue": "2000003",
382 "UMask": "0x4"
383 },
384 {
385 "BriefDescription": "Number of times we could not allocate Lock Buffer",
386 "Counter": "0,1,2,3",
387 "EventCode": "0x54",
388 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
389 "PublicDescription": "Number of times we could not allocate Lock Buffer.",
390 "SampleAfterValue": "2000003",
391 "UMask": "0x40"
392 }
393 ]
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.