1 [
2 {
3 "BriefDescription": "L1D data line replacements",
4 "Counter": "0,1,2,3",
5 "EventCode": "0x51",
6 "EventName": "L1D.REPLACEMENT",
7 "PublicDescription": "Counts the number of lines brought into the L1 data cache.",
8 "SampleAfterValue": "2000003",
9 "UMask": "0x1"
10 },
11 {
12 "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability",
13 "Counter": "0,1,2,3",
14 "CounterMask": "1",
15 "EventCode": "0x48",
16 "EventName": "L1D_PEND_MISS.FB_FULL",
17 "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.",
18 "SampleAfterValue": "2000003",
19 "UMask": "0x2"
20 },
21 {
22 "BriefDescription": "L1D miss outstanding duration in cycles",
23 "Counter": "2",
24 "EventCode": "0x48",
25 "EventName": "L1D_PEND_MISS.PENDING",
26 "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
27 "SampleAfterValue": "2000003",
28 "UMask": "0x1"
29 },
30 {
31 "BriefDescription": "Cycles with L1D load Misses outstanding.",
32 "Counter": "2",
33 "CounterMask": "1",
34 "EventCode": "0x48",
35 "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
36 "SampleAfterValue": "2000003",
37 "UMask": "0x1"
38 },
39 {
40 "AnyThread": "1",
41 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",
42 "Counter": "2",
43 "CounterMask": "1",
44 "EventCode": "0x48",
45 "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
46 "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
47 "SampleAfterValue": "2000003",
48 "UMask": "0x1"
49 },
50 {
51 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
52 "Counter": "0,1,2,3",
53 "EventCode": "0x28",
54 "EventName": "L2_L1D_WB_RQSTS.ALL",
55 "SampleAfterValue": "200003",
56 "UMask": "0xf"
57 },
58 {
59 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
60 "Counter": "0,1,2,3",
61 "EventCode": "0x28",
62 "EventName": "L2_L1D_WB_RQSTS.HIT_E",
63 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
64 "SampleAfterValue": "200003",
65 "UMask": "0x4"
66 },
67 {
68 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
69 "Counter": "0,1,2,3",
70 "EventCode": "0x28",
71 "EventName": "L2_L1D_WB_RQSTS.HIT_M",
72 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
73 "SampleAfterValue": "200003",
74 "UMask": "0x8"
75 },
76 {
77 "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)",
78 "Counter": "0,1,2,3",
79 "EventCode": "0x28",
80 "EventName": "L2_L1D_WB_RQSTS.MISS",
81 "PublicDescription": "Not rejected writebacks that missed LLC.",
82 "SampleAfterValue": "200003",
83 "UMask": "0x1"
84 },
85 {
86 "BriefDescription": "L2 cache lines filling L2",
87 "Counter": "0,1,2,3",
88 "EventCode": "0xF1",
89 "EventName": "L2_LINES_IN.ALL",
90 "PublicDescription": "L2 cache lines filling L2.",
91 "SampleAfterValue": "100003",
92 "UMask": "0x7"
93 },
94 {
95 "BriefDescription": "L2 cache lines in E state filling L2",
96 "Counter": "0,1,2,3",
97 "EventCode": "0xF1",
98 "EventName": "L2_LINES_IN.E",
99 "PublicDescription": "L2 cache lines in E state filling L2.",
100 "SampleAfterValue": "100003",
101 "UMask": "0x4"
102 },
103 {
104 "BriefDescription": "L2 cache lines in I state filling L2",
105 "Counter": "0,1,2,3",
106 "EventCode": "0xF1",
107 "EventName": "L2_LINES_IN.I",
108 "PublicDescription": "L2 cache lines in I state filling L2.",
109 "SampleAfterValue": "100003",
110 "UMask": "0x1"
111 },
112 {
113 "BriefDescription": "L2 cache lines in S state filling L2",
114 "Counter": "0,1,2,3",
115 "EventCode": "0xF1",
116 "EventName": "L2_LINES_IN.S",
117 "PublicDescription": "L2 cache lines in S state filling L2.",
118 "SampleAfterValue": "100003",
119 "UMask": "0x2"
120 },
121 {
122 "BriefDescription": "Clean L2 cache lines evicted by demand",
123 "Counter": "0,1,2,3",
124 "EventCode": "0xF2",
125 "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
126 "PublicDescription": "Clean L2 cache lines evicted by demand.",
127 "SampleAfterValue": "100003",
128 "UMask": "0x1"
129 },
130 {
131 "BriefDescription": "Dirty L2 cache lines evicted by demand",
132 "Counter": "0,1,2,3",
133 "EventCode": "0xF2",
134 "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
135 "PublicDescription": "Dirty L2 cache lines evicted by demand.",
136 "SampleAfterValue": "100003",
137 "UMask": "0x2"
138 },
139 {
140 "BriefDescription": "Dirty L2 cache lines filling the L2",
141 "Counter": "0,1,2,3",
142 "EventCode": "0xF2",
143 "EventName": "L2_LINES_OUT.DIRTY_ALL",
144 "PublicDescription": "Dirty L2 cache lines filling the L2.",
145 "SampleAfterValue": "100003",
146 "UMask": "0xa"
147 },
148 {
149 "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch",
150 "Counter": "0,1,2,3",
151 "EventCode": "0xF2",
152 "EventName": "L2_LINES_OUT.PF_CLEAN",
153 "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.",
154 "SampleAfterValue": "100003",
155 "UMask": "0x4"
156 },
157 {
158 "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch",
159 "Counter": "0,1,2,3",
160 "EventCode": "0xF2",
161 "EventName": "L2_LINES_OUT.PF_DIRTY",
162 "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.",
163 "SampleAfterValue": "100003",
164 "UMask": "0x8"
165 },
166 {
167 "BriefDescription": "L2 code requests",
168 "Counter": "0,1,2,3",
169 "EventCode": "0x24",
170 "EventName": "L2_RQSTS.ALL_CODE_RD",
171 "PublicDescription": "Counts all L2 code requests.",
172 "SampleAfterValue": "200003",
173 "UMask": "0x30"
174 },
175 {
176 "BriefDescription": "Demand Data Read requests",
177 "Counter": "0,1,2,3",
178 "EventCode": "0x24",
179 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
180 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
181 "SampleAfterValue": "200003",
182 "UMask": "0x3"
183 },
184 {
185 "BriefDescription": "Requests from L2 hardware prefetchers",
186 "Counter": "0,1,2,3",
187 "EventCode": "0x24",
188 "EventName": "L2_RQSTS.ALL_PF",
189 "PublicDescription": "Counts all L2 HW prefetcher requests.",
190 "SampleAfterValue": "200003",
191 "UMask": "0xc0"
192 },
193 {
194 "BriefDescription": "RFO requests to L2 cache",
195 "Counter": "0,1,2,3",
196 "EventCode": "0x24",
197 "EventName": "L2_RQSTS.ALL_RFO",
198 "PublicDescription": "Counts all L2 store RFO requests.",
199 "SampleAfterValue": "200003",
200 "UMask": "0xc"
201 },
202 {
203 "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
204 "Counter": "0,1,2,3",
205 "EventCode": "0x24",
206 "EventName": "L2_RQSTS.CODE_RD_HIT",
207 "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
208 "SampleAfterValue": "200003",
209 "UMask": "0x10"
210 },
211 {
212 "BriefDescription": "L2 cache misses when fetching instructions",
213 "Counter": "0,1,2,3",
214 "EventCode": "0x24",
215 "EventName": "L2_RQSTS.CODE_RD_MISS",
216 "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
217 "SampleAfterValue": "200003",
218 "UMask": "0x20"
219 },
220 {
221 "BriefDescription": "Demand Data Read requests that hit L2 cache",
222 "Counter": "0,1,2,3",
223 "EventCode": "0x24",
224 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
225 "PublicDescription": "Demand Data Read requests that hit L2 cache.",
226 "SampleAfterValue": "200003",
227 "UMask": "0x1"
228 },
229 {
230 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",
231 "Counter": "0,1,2,3",
232 "EventCode": "0x24",
233 "EventName": "L2_RQSTS.PF_HIT",
234 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
235 "SampleAfterValue": "200003",
236 "UMask": "0x40"
237 },
238 {
239 "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",
240 "Counter": "0,1,2,3",
241 "EventCode": "0x24",
242 "EventName": "L2_RQSTS.PF_MISS",
243 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
244 "SampleAfterValue": "200003",
245 "UMask": "0x80"
246 },
247 {
248 "BriefDescription": "RFO requests that hit L2 cache",
249 "Counter": "0,1,2,3",
250 "EventCode": "0x24",
251 "EventName": "L2_RQSTS.RFO_HIT",
252 "PublicDescription": "RFO requests that hit L2 cache.",
253 "SampleAfterValue": "200003",
254 "UMask": "0x4"
255 },
256 {
257 "BriefDescription": "RFO requests that miss L2 cache",
258 "Counter": "0,1,2,3",
259 "EventCode": "0x24",
260 "EventName": "L2_RQSTS.RFO_MISS",
261 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
262 "SampleAfterValue": "200003",
263 "UMask": "0x8"
264 },
265 {
266 "BriefDescription": "RFOs that access cache lines in any state",
267 "Counter": "0,1,2,3",
268 "EventCode": "0x27",
269 "EventName": "L2_STORE_LOCK_RQSTS.ALL",
270 "PublicDescription": "RFOs that access cache lines in any state.",
271 "SampleAfterValue": "200003",
272 "UMask": "0xf"
273 },
274 {
275 "BriefDescription": "RFOs that hit cache lines in M state",
276 "Counter": "0,1,2,3",
277 "EventCode": "0x27",
278 "EventName": "L2_STORE_LOCK_RQSTS.HIT_M",
279 "PublicDescription": "RFOs that hit cache lines in M state.",
280 "SampleAfterValue": "200003",
281 "UMask": "0x8"
282 },
283 {
284 "BriefDescription": "RFOs that miss cache lines",
285 "Counter": "0,1,2,3",
286 "EventCode": "0x27",
287 "EventName": "L2_STORE_LOCK_RQSTS.MISS",
288 "PublicDescription": "RFOs that miss cache lines.",
289 "SampleAfterValue": "200003",
290 "UMask": "0x1"
291 },
292 {
293 "BriefDescription": "L2 or LLC HW prefetches that access L2 cache",
294 "Counter": "0,1,2,3",
295 "EventCode": "0xF0",
296 "EventName": "L2_TRANS.ALL_PF",
297 "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.",
298 "SampleAfterValue": "200003",
299 "UMask": "0x8"
300 },
301 {
302 "BriefDescription": "Transactions accessing L2 pipe",
303 "Counter": "0,1,2,3",
304 "EventCode": "0xF0",
305 "EventName": "L2_TRANS.ALL_REQUESTS",
306 "PublicDescription": "Transactions accessing L2 pipe.",
307 "SampleAfterValue": "200003",
308 "UMask": "0x80"
309 },
310 {
311 "BriefDescription": "L2 cache accesses when fetching instructions",
312 "Counter": "0,1,2,3",
313 "EventCode": "0xF0",
314 "EventName": "L2_TRANS.CODE_RD",
315 "PublicDescription": "L2 cache accesses when fetching instructions.",
316 "SampleAfterValue": "200003",
317 "UMask": "0x4"
318 },
319 {
320 "BriefDescription": "Demand Data Read requests that access L2 cache",
321 "Counter": "0,1,2,3",
322 "EventCode": "0xF0",
323 "EventName": "L2_TRANS.DEMAND_DATA_RD",
324 "PublicDescription": "Demand Data Read requests that access L2 cache.",
325 "SampleAfterValue": "200003",
326 "UMask": "0x1"
327 },
328 {
329 "BriefDescription": "L1D writebacks that access L2 cache",
330 "Counter": "0,1,2,3",
331 "EventCode": "0xF0",
332 "EventName": "L2_TRANS.L1D_WB",
333 "PublicDescription": "L1D writebacks that access L2 cache.",
334 "SampleAfterValue": "200003",
335 "UMask": "0x10"
336 },
337 {
338 "BriefDescription": "L2 fill requests that access L2 cache",
339 "Counter": "0,1,2,3",
340 "EventCode": "0xF0",
341 "EventName": "L2_TRANS.L2_FILL",
342 "PublicDescription": "L2 fill requests that access L2 cache.",
343 "SampleAfterValue": "200003",
344 "UMask": "0x20"
345 },
346 {
347 "BriefDescription": "L2 writebacks that access L2 cache",
348 "Counter": "0,1,2,3",
349 "EventCode": "0xF0",
350 "EventName": "L2_TRANS.L2_WB",
351 "PublicDescription": "L2 writebacks that access L2 cache.",
352 "SampleAfterValue": "200003",
353 "UMask": "0x40"
354 },
355 {
356 "BriefDescription": "RFO requests that access L2 cache",
357 "Counter": "0,1,2,3",
358 "EventCode": "0xF0",
359 "EventName": "L2_TRANS.RFO",
360 "PublicDescription": "RFO requests that access L2 cache.",
361 "SampleAfterValue": "200003",
362 "UMask": "0x2"
363 },
364 {
365 "BriefDescription": "Cycles when L1D is locked",
366 "Counter": "0,1,2,3",
367 "EventCode": "0x63",
368 "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
369 "PublicDescription": "Cycles in which the L1D is locked.",
370 "SampleAfterValue": "2000003",
371 "UMask": "0x2"
372 },
373 {
374 "BriefDescription": "Core-originated cacheable demand requests missed LLC",
375 "Counter": "0,1,2,3",
376 "EventCode": "0x2E",
377 "EventName": "LONGEST_LAT_CACHE.MISS",
378 "PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
379 "SampleAfterValue": "100003",
380 "UMask": "0x41"
381 },
382 {
383 "BriefDescription": "Core-originated cacheable demand requests that refer to LLC",
384 "Counter": "0,1,2,3",
385 "EventCode": "0x2E",
386 "EventName": "LONGEST_LAT_CACHE.REFERENCE",
387 "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
388 "SampleAfterValue": "100003",
389 "UMask": "0x4f"
390 },
391 {
392 "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.",
393 "Counter": "0,1,2,3",
394 "EventCode": "0xD2",
395 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",
396 "PEBS": "1",
397 "SampleAfterValue": "20011",
398 "UMask": "0x2"
399 },
400 {
401 "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.",
402 "Counter": "0,1,2,3",
403 "EventCode": "0xD2",
404 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",
405 "PEBS": "1",
406 "SampleAfterValue": "20011",
407 "UMask": "0x4"
408 },
409 {
410 "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.",
411 "Counter": "0,1,2,3",
412 "EventCode": "0xD2",
413 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",
414 "PEBS": "1",
415 "SampleAfterValue": "20011",
416 "UMask": "0x1"
417 },
418 {
419 "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.",
420 "Counter": "0,1,2,3",
421 "EventCode": "0xD2",
422 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",
423 "PEBS": "1",
424 "SampleAfterValue": "100003",
425 "UMask": "0x8"
426 },
427 {
428 "BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.",
429 "Counter": "0,1,2,3",
430 "EventCode": "0xD3",
431 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",
432 "PublicDescription": "Retired load uops whose data source was local memory (cross-socket snoop not needed or missed).",
433 "SampleAfterValue": "100007",
434 "UMask": "0x1"
435 },
436 {
437 "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
438 "Counter": "0,1,2,3",
439 "EventCode": "0xD1",
440 "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
441 "PEBS": "1",
442 "SampleAfterValue": "100003",
443 "UMask": "0x40"
444 },
445 {
446 "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
447 "Counter": "0,1,2,3",
448 "EventCode": "0xD1",
449 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
450 "PEBS": "1",
451 "SampleAfterValue": "2000003",
452 "UMask": "0x1"
453 },
454 {
455 "BriefDescription": "Retired load uops which data sources following L1 data-cache miss.",
456 "Counter": "0,1,2,3",
457 "EventCode": "0xD1",
458 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
459 "PEBS": "1",
460 "SampleAfterValue": "100003",
461 "UMask": "0x8"
462 },
463 {
464 "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
465 "Counter": "0,1,2,3",
466 "EventCode": "0xD1",
467 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
468 "PEBS": "1",
469 "SampleAfterValue": "100003",
470 "UMask": "0x2"
471 },
472 {
473 "BriefDescription": "Retired load uops with L2 cache misses as data sources.",
474 "Counter": "0,1,2,3",
475 "EventCode": "0xD1",
476 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
477 "PEBS": "1",
478 "SampleAfterValue": "50021",
479 "UMask": "0x10"
480 },
481 {
482 "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.",
483 "Counter": "0,1,2,3",
484 "EventCode": "0xD1",
485 "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",
486 "PEBS": "1",
487 "SampleAfterValue": "50021",
488 "UMask": "0x4"
489 },
490 {
491 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
492 "Counter": "0,1,2,3",
493 "EventCode": "0xD1",
494 "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS",
495 "PEBS": "1",
496 "SampleAfterValue": "100007",
497 "UMask": "0x20"
498 },
499 {
500 "BriefDescription": "All retired load uops. (Precise Event)",
501 "Counter": "0,1,2,3",
502 "EventCode": "0xD0",
503 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
504 "PEBS": "1",
505 "SampleAfterValue": "2000003",
506 "UMask": "0x81"
507 },
508 {
509 "BriefDescription": "All retired store uops. (Precise Event)",
510 "Counter": "0,1,2,3",
511 "EventCode": "0xD0",
512 "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
513 "PEBS": "1",
514 "SampleAfterValue": "2000003",
515 "UMask": "0x82"
516 },
517 {
518 "BriefDescription": "Retired load uops with locked access. (Precise Event)",
519 "Counter": "0,1,2,3",
520 "EventCode": "0xD0",
521 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
522 "PEBS": "1",
523 "SampleAfterValue": "100007",
524 "UMask": "0x21"
525 },
526 {
527 "BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event)",
528 "Counter": "0,1,2,3",
529 "EventCode": "0xD0",
530 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
531 "PEBS": "1",
532 "SampleAfterValue": "100003",
533 "UMask": "0x41"
534 },
535 {
536 "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event)",
537 "Counter": "0,1,2,3",
538 "EventCode": "0xD0",
539 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
540 "PEBS": "1",
541 "SampleAfterValue": "100003",
542 "UMask": "0x42"
543 },
544 {
545 "BriefDescription": "Retired load uops that miss the STLB. (Precise Event)",
546 "Counter": "0,1,2,3",
547 "EventCode": "0xD0",
548 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
549 "PEBS": "1",
550 "SampleAfterValue": "100003",
551 "UMask": "0x11"
552 },
553 {
554 "BriefDescription": "Retired store uops that miss the STLB. (Precise Event)",
555 "Counter": "0,1,2,3",
556 "EventCode": "0xD0",
557 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
558 "PEBS": "1",
559 "SampleAfterValue": "100003",
560 "UMask": "0x12"
561 },
562 {
563 "BriefDescription": "Demand and prefetch data reads",
564 "Counter": "0,1,2,3",
565 "EventCode": "0xB0",
566 "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
567 "PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
568 "SampleAfterValue": "100003",
569 "UMask": "0x8"
570 },
571 {
572 "BriefDescription": "Cacheable and noncacheable code read requests",
573 "Counter": "0,1,2,3",
574 "EventCode": "0xB0",
575 "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
576 "PublicDescription": "Demand code read requests sent to uncore.",
577 "SampleAfterValue": "100003",
578 "UMask": "0x2"
579 },
580 {
581 "BriefDescription": "Demand Data Read requests sent to uncore",
582 "Counter": "0,1,2,3",
583 "EventCode": "0xB0",
584 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
585 "PublicDescription": "Demand data read requests sent to uncore.",
586 "SampleAfterValue": "100003",
587 "UMask": "0x1"
588 },
589 {
590 "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
591 "Counter": "0,1,2,3",
592 "EventCode": "0xB0",
593 "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
594 "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
595 "SampleAfterValue": "100003",
596 "UMask": "0x4"
597 },
598 {
599 "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core",
600 "Counter": "0,1,2,3",
601 "EventCode": "0xB2",
602 "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
603 "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.",
604 "SampleAfterValue": "2000003",
605 "UMask": "0x1"
606 },
607 {
608 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
609 "Counter": "0,1,2,3",
610 "EventCode": "0x60",
611 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
612 "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
613 "SampleAfterValue": "2000003",
614 "UMask": "0x8"
615 },
616 {
617 "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
618 "Counter": "0,1,2,3",
619 "CounterMask": "1",
620 "EventCode": "0x60",
621 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
622 "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
623 "SampleAfterValue": "2000003",
624 "UMask": "0x8"
625 },
626 {
627 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
628 "Counter": "0,1,2,3",
629 "CounterMask": "1",
630 "EventCode": "0x60",
631 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
632 "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
633 "SampleAfterValue": "2000003",
634 "UMask": "0x2"
635 },
636 {
637 "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
638 "Counter": "0,1,2,3",
639 "CounterMask": "1",
640 "EventCode": "0x60",
641 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
642 "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
643 "SampleAfterValue": "2000003",
644 "UMask": "0x1"
645 },
646 {
647 "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
648 "Counter": "0,1,2,3",
649 "CounterMask": "1",
650 "EventCode": "0x60",
651 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
652 "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
653 "SampleAfterValue": "2000003",
654 "UMask": "0x4"
655 },
656 {
657 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
658 "Counter": "0,1,2,3",
659 "EventCode": "0x60",
660 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
661 "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
662 "SampleAfterValue": "2000003",
663 "UMask": "0x2"
664 },
665 {
666 "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
667 "Counter": "0,1,2,3",
668 "EventCode": "0x60",
669 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
670 "PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
671 "SampleAfterValue": "2000003",
672 "UMask": "0x1"
673 },
674 {
675 "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",
676 "Counter": "0,1,2,3",
677 "CounterMask": "6",
678 "EventCode": "0x60",
679 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
680 "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
681 "SampleAfterValue": "2000003",
682 "UMask": "0x1"
683 },
684 {
685 "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
686 "Counter": "0,1,2,3",
687 "EventCode": "0x60",
688 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
689 "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",
690 "SampleAfterValue": "2000003",
691 "UMask": "0x4"
692 },
693 {
694 "BriefDescription": "Counts all demand & prefetch code reads that hit in the LLC",
695 "Counter": "0,1,2,3",
696 "EventCode": "0xB7, 0xBB",
697 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE",
698 "MSRIndex": "0x1a6,0x1a7",
699 "MSRValue": "0x3f803c0244",
700 "SampleAfterValue": "100003",
701 "UMask": "0x1"
702 },
703 {
704 "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
705 "Counter": "0,1,2,3",
706 "EventCode": "0xB7, 0xBB",
707 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
708 "MSRIndex": "0x1a6,0x1a7",
709 "MSRValue": "0x1003c0244",
710 "SampleAfterValue": "100003",
711 "UMask": "0x1"
712 },
713 {
714 "BriefDescription": "Counts all demand & prefetch data reads",
715 "Counter": "0,1,2,3",
716 "EventCode": "0xB7, 0xBB",
717 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",
718 "MSRIndex": "0x1a6,0x1a7",
719 "MSRValue": "0x000105B3",
720 "SampleAfterValue": "100003",
721 "UMask": "0x1"
722 },
723 {
724 "BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC",
725 "Counter": "0,1,2,3",
726 "EventCode": "0xB7, 0xBB",
727 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE",
728 "MSRIndex": "0x1a6,0x1a7",
729 "MSRValue": "0x3f803c0091",
730 "SampleAfterValue": "100003",
731 "UMask": "0x1"
732 },
733 {
734 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
735 "Counter": "0,1,2,3",
736 "EventCode": "0xB7, 0xBB",
737 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
738 "MSRIndex": "0x1a6,0x1a7",
739 "MSRValue": "0x10003c0091",
740 "SampleAfterValue": "100003",
741 "UMask": "0x1"
742 },
743 {
744 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
745 "Counter": "0,1,2,3",
746 "EventCode": "0xB7, 0xBB",
747 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
748 "MSRIndex": "0x1a6,0x1a7",
749 "MSRValue": "0x4003c0091",
750 "SampleAfterValue": "100003",
751 "UMask": "0x1"
752 },
753 {
754 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
755 "Counter": "0,1,2,3",
756 "EventCode": "0xB7, 0xBB",
757 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
758 "MSRIndex": "0x1a6,0x1a7",
759 "MSRValue": "0x1003c0091",
760 "SampleAfterValue": "100003",
761 "UMask": "0x1"
762 },
763 {
764 "BriefDescription": "Counts all data/code/rfo references (demand & prefetch)",
765 "Counter": "0,1,2,3",
766 "EventCode": "0xB7, 0xBB",
767 "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE",
768 "MSRIndex": "0x1a6,0x1a7",
769 "MSRValue": "0x000107F7",
770 "SampleAfterValue": "100003",
771 "UMask": "0x1"
772 },
773 {
774 "BriefDescription": "Counts all demand & prefetch prefetch RFOs",
775 "Counter": "0,1,2,3",
776 "EventCode": "0xB7, 0xBB",
777 "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
778 "MSRIndex": "0x1a6,0x1a7",
779 "MSRValue": "0x00010122",
780 "SampleAfterValue": "100003",
781 "UMask": "0x1"
782 },
783 {
784 "BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC",
785 "Counter": "0,1,2,3",
786 "EventCode": "0xB7, 0xBB",
787 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE",
788 "MSRIndex": "0x1a6,0x1a7",
789 "MSRValue": "0x3f803c0122",
790 "SampleAfterValue": "100003",
791 "UMask": "0x1"
792 },
793 {
794 "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
795 "Counter": "0,1,2,3",
796 "EventCode": "0xB7, 0xBB",
797 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED",
798 "MSRIndex": "0x1a6,0x1a7",
799 "MSRValue": "0x1003c0122",
800 "SampleAfterValue": "100003",
801 "UMask": "0x1"
802 },
803 {
804 "BriefDescription": "Counts all writebacks from the core to the LLC",
805 "Counter": "0,1,2,3",
806 "EventCode": "0xB7, 0xBB",
807 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
808 "MSRIndex": "0x1a6,0x1a7",
809 "MSRValue": "0x10008",
810 "SampleAfterValue": "100003",
811 "UMask": "0x1"
812 },
813 {
814 "BriefDescription": "Counts all demand code reads",
815 "Counter": "0,1,2,3",
816 "EventCode": "0xB7, 0xBB",
817 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
818 "MSRIndex": "0x1a6,0x1a7",
819 "MSRValue": "0x00010004",
820 "SampleAfterValue": "100003",
821 "UMask": "0x1"
822 },
823 {
824 "BriefDescription": "Counts all demand code reads that hit in the LLC",
825 "Counter": "0,1,2,3",
826 "EventCode": "0xB7, 0xBB",
827 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
828 "MSRIndex": "0x1a6,0x1a7",
829 "MSRValue": "0x3f803c0004",
830 "SampleAfterValue": "100003",
831 "UMask": "0x1"
832 },
833 {
834 "BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
835 "Counter": "0,1,2,3",
836 "EventCode": "0xB7, 0xBB",
837 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
838 "MSRIndex": "0x1a6,0x1a7",
839 "MSRValue": "0x1003c0004",
840 "SampleAfterValue": "100003",
841 "UMask": "0x1"
842 },
843 {
844 "BriefDescription": "Counts all demand data reads",
845 "Counter": "0,1,2,3",
846 "EventCode": "0xB7, 0xBB",
847 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
848 "MSRIndex": "0x1a6,0x1a7",
849 "MSRValue": "0x00010001",
850 "SampleAfterValue": "100003",
851 "UMask": "0x1"
852 },
853 {
854 "BriefDescription": "Counts all demand data reads that hit in the LLC",
855 "Counter": "0,1,2,3",
856 "EventCode": "0xB7, 0xBB",
857 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
858 "MSRIndex": "0x1a6,0x1a7",
859 "MSRValue": "0x3f803c0001",
860 "SampleAfterValue": "100003",
861 "UMask": "0x1"
862 },
863 {
864 "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
865 "Counter": "0,1,2,3",
866 "EventCode": "0xB7, 0xBB",
867 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
868 "MSRIndex": "0x1a6,0x1a7",
869 "MSRValue": "0x10003c0001",
870 "SampleAfterValue": "100003",
871 "UMask": "0x1"
872 },
873 {
874 "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
875 "Counter": "0,1,2,3",
876 "EventCode": "0xB7, 0xBB",
877 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
878 "MSRIndex": "0x1a6,0x1a7",
879 "MSRValue": "0x4003c0001",
880 "SampleAfterValue": "100003",
881 "UMask": "0x1"
882 },
883 {
884 "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
885 "Counter": "0,1,2,3",
886 "EventCode": "0xB7, 0xBB",
887 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
888 "MSRIndex": "0x1a6,0x1a7",
889 "MSRValue": "0x1003c0001",
890 "SampleAfterValue": "100003",
891 "UMask": "0x1"
892 },
893 {
894 "BriefDescription": "Counts all demand rfo's",
895 "Counter": "0,1,2,3",
896 "EventCode": "0xB7, 0xBB",
897 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
898 "MSRIndex": "0x1a6,0x1a7",
899 "MSRValue": "0x00010002",
900 "SampleAfterValue": "100003",
901 "UMask": "0x1"
902 },
903 {
904 "BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC",
905 "Counter": "0,1,2,3",
906 "EventCode": "0xB7, 0xBB",
907 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE",
908 "MSRIndex": "0x1a6,0x1a7",
909 "MSRValue": "0x3f803c0002",
910 "SampleAfterValue": "100003",
911 "UMask": "0x1"
912 },
913 {
914 "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
915 "Counter": "0,1,2,3",
916 "EventCode": "0xB7, 0xBB",
917 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
918 "MSRIndex": "0x1a6,0x1a7",
919 "MSRValue": "0x10003c0002",
920 "SampleAfterValue": "100003",
921 "UMask": "0x1"
922 },
923 {
924 "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
925 "Counter": "0,1,2,3",
926 "EventCode": "0xB7, 0xBB",
927 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED",
928 "MSRIndex": "0x1a6,0x1a7",
929 "MSRValue": "0x1003c0002",
930 "SampleAfterValue": "100003",
931 "UMask": "0x1"
932 },
933 {
934 "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches",
935 "Counter": "0,1,2,3",
936 "EventCode": "0xB7, 0xBB",
937 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",
938 "MSRIndex": "0x1a6,0x1a7",
939 "MSRValue": "0x18000",
940 "SampleAfterValue": "100003",
941 "UMask": "0x1"
942 },
943 {
944 "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",
945 "Counter": "0,1,2,3",
946 "EventCode": "0xB7, 0xBB",
947 "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
948 "MSRIndex": "0x1a6,0x1a7",
949 "MSRValue": "0x10400",
950 "SampleAfterValue": "100003",
951 "UMask": "0x1"
952 },
953 {
954 "BriefDescription": "Counts non-temporal stores",
955 "Counter": "0,1,2,3",
956 "EventCode": "0xB7, 0xBB",
957 "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
958 "MSRIndex": "0x1a6,0x1a7",
959 "MSRValue": "0x10800",
960 "SampleAfterValue": "100003",
961 "UMask": "0x1"
962 },
963 {
964 "BriefDescription": "Split locks in SQ",
965 "Counter": "0,1,2,3",
966 "EventCode": "0xF4",
967 "EventName": "SQ_MISC.SPLIT_LOCK",
968 "SampleAfterValue": "100003",
969 "UMask": "0x10"
970 }
971 ]
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