1 [
2 {
3 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
4 "Counter": "0,1,2,3",
5 "EventCode": "0xC3",
6 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
7 "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.",
8 "SampleAfterValue": "100003",
9 "UMask": "0x2"
10 },
11 {
12 "BriefDescription": "Loads with latency value being above 128.",
13 "Counter": "3",
14 "EventCode": "0xCD",
15 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
16 "MSRIndex": "0x3F6",
17 "MSRValue": "0x80",
18 "PEBS": "2",
19 "SampleAfterValue": "1009",
20 "UMask": "0x1"
21 },
22 {
23 "BriefDescription": "Loads with latency value being above 16.",
24 "Counter": "3",
25 "EventCode": "0xCD",
26 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
27 "MSRIndex": "0x3F6",
28 "MSRValue": "0x10",
29 "PEBS": "2",
30 "SampleAfterValue": "20011",
31 "UMask": "0x1"
32 },
33 {
34 "BriefDescription": "Loads with latency value being above 256.",
35 "Counter": "3",
36 "EventCode": "0xCD",
37 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
38 "MSRIndex": "0x3F6",
39 "MSRValue": "0x100",
40 "PEBS": "2",
41 "SampleAfterValue": "503",
42 "UMask": "0x1"
43 },
44 {
45 "BriefDescription": "Loads with latency value being above 32.",
46 "Counter": "3",
47 "EventCode": "0xCD",
48 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
49 "MSRIndex": "0x3F6",
50 "MSRValue": "0x20",
51 "PEBS": "2",
52 "SampleAfterValue": "100007",
53 "UMask": "0x1"
54 },
55 {
56 "BriefDescription": "Loads with latency value being above 4 .",
57 "Counter": "3",
58 "EventCode": "0xCD",
59 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
60 "MSRIndex": "0x3F6",
61 "MSRValue": "0x4",
62 "PEBS": "2",
63 "SampleAfterValue": "100003",
64 "UMask": "0x1"
65 },
66 {
67 "BriefDescription": "Loads with latency value being above 512.",
68 "Counter": "3",
69 "EventCode": "0xCD",
70 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
71 "MSRIndex": "0x3F6",
72 "MSRValue": "0x200",
73 "PEBS": "2",
74 "SampleAfterValue": "101",
75 "UMask": "0x1"
76 },
77 {
78 "BriefDescription": "Loads with latency value being above 64.",
79 "Counter": "3",
80 "EventCode": "0xCD",
81 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
82 "MSRIndex": "0x3F6",
83 "MSRValue": "0x40",
84 "PEBS": "2",
85 "SampleAfterValue": "2003",
86 "UMask": "0x1"
87 },
88 {
89 "BriefDescription": "Loads with latency value being above 8.",
90 "Counter": "3",
91 "EventCode": "0xCD",
92 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
93 "MSRIndex": "0x3F6",
94 "MSRValue": "0x8",
95 "PEBS": "2",
96 "SampleAfterValue": "50021",
97 "UMask": "0x1"
98 },
99 {
100 "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).",
101 "Counter": "3",
102 "EventCode": "0xCD",
103 "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
104 "PEBS": "2",
105 "SampleAfterValue": "2000003",
106 "UMask": "0x2"
107 },
108 {
109 "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.",
110 "Counter": "0,1,2,3",
111 "EventCode": "0x05",
112 "EventName": "MISALIGN_MEM_REF.LOADS",
113 "SampleAfterValue": "2000003",
114 "UMask": "0x1"
115 },
116 {
117 "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.",
118 "Counter": "0,1,2,3",
119 "EventCode": "0x05",
120 "EventName": "MISALIGN_MEM_REF.STORES",
121 "SampleAfterValue": "2000003",
122 "UMask": "0x2"
123 },
124 {
125 "BriefDescription": "This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded.",
126 "Counter": "0,1,2,3",
127 "EventCode": "0xB7, 0xBB",
128 "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.ANY_RESPONSE",
129 "MSRIndex": "0x1a6,0x1a7",
130 "MSRValue": "0x3FFFC20077",
131 "SampleAfterValue": "100003",
132 "UMask": "0x1"
133 },
134 {
135 "BriefDescription": "Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded.",
136 "Counter": "0,1,2,3",
137 "EventCode": "0xB7, 0xBB",
138 "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.LOCAL_DRAM",
139 "MSRIndex": "0x1a6,0x1a7",
140 "MSRValue": "0x600400077",
141 "SampleAfterValue": "100003",
142 "UMask": "0x1"
143 },
144 {
145 "BriefDescription": "This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded.",
146 "Counter": "0,1,2,3",
147 "EventCode": "0xB7, 0xBB",
148 "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.REMOTE_HITM_HIT_FORWARD",
149 "MSRIndex": "0x1a6,0x1a7",
150 "MSRValue": "0x187FC20077",
151 "SampleAfterValue": "100003",
152 "UMask": "0x1"
153 },
154 {
155 "BriefDescription": "Counts all demand code reads that miss the LLC",
156 "Counter": "0,1,2,3",
157 "EventCode": "0xB7, 0xBB",
158 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",
159 "MSRIndex": "0x1a6,0x1a7",
160 "MSRValue": "0x3fffc20004",
161 "SampleAfterValue": "100003",
162 "UMask": "0x1"
163 },
164 {
165 "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from local dram",
166 "Counter": "0,1,2,3",
167 "EventCode": "0xB7, 0xBB",
168 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",
169 "MSRIndex": "0x1a6,0x1a7",
170 "MSRValue": "0x600400004",
171 "SampleAfterValue": "100003",
172 "UMask": "0x1"
173 },
174 {
175 "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from remote dram",
176 "Counter": "0,1,2,3",
177 "EventCode": "0xB7, 0xBB",
178 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM",
179 "MSRIndex": "0x1a6,0x1a7",
180 "MSRValue": "0x67f800004",
181 "SampleAfterValue": "100003",
182 "UMask": "0x1"
183 },
184 {
185 "BriefDescription": "Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
186 "Counter": "0,1,2,3",
187 "EventCode": "0xB7, 0xBB",
188 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM",
189 "MSRIndex": "0x1a6,0x1a7",
190 "MSRValue": "0x107fc00004",
191 "SampleAfterValue": "100003",
192 "UMask": "0x1"
193 },
194 {
195 "BriefDescription": "Counts all demand code reads that miss the LLC and the data forwarded from remote cache",
196 "Counter": "0,1,2,3",
197 "EventCode": "0xB7, 0xBB",
198 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD",
199 "MSRIndex": "0x1a6,0x1a7",
200 "MSRValue": "0x87f820004",
201 "SampleAfterValue": "100003",
202 "UMask": "0x1"
203 },
204 {
205 "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote & local dram",
206 "Counter": "0,1,2,3",
207 "EventCode": "0xB7, 0xBB",
208 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM",
209 "MSRIndex": "0x1a6,0x1a7",
210 "MSRValue": "0x67fc00001",
211 "SampleAfterValue": "100003",
212 "UMask": "0x1"
213 },
214 {
215 "BriefDescription": "Counts demand data reads that miss in the LLC",
216 "Counter": "0,1,2,3",
217 "EventCode": "0xB7, 0xBB",
218 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",
219 "MSRIndex": "0x1a6,0x1a7",
220 "MSRValue": "0x3fffc20001",
221 "SampleAfterValue": "100003",
222 "UMask": "0x1"
223 },
224 {
225 "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from local dram",
226 "Counter": "0,1,2,3",
227 "EventCode": "0xB7, 0xBB",
228 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",
229 "MSRIndex": "0x1a6,0x1a7",
230 "MSRValue": "0x600400001",
231 "SampleAfterValue": "100003",
232 "UMask": "0x1"
233 },
234 {
235 "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote dram",
236 "Counter": "0,1,2,3",
237 "EventCode": "0xB7, 0xBB",
238 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM",
239 "MSRIndex": "0x1a6,0x1a7",
240 "MSRValue": "0x67f800001",
241 "SampleAfterValue": "100003",
242 "UMask": "0x1"
243 },
244 {
245 "BriefDescription": "Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
246 "Counter": "0,1,2,3",
247 "EventCode": "0xB7, 0xBB",
248 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM",
249 "MSRIndex": "0x1a6,0x1a7",
250 "MSRValue": "0x107fc00001",
251 "SampleAfterValue": "100003",
252 "UMask": "0x1"
253 },
254 {
255 "BriefDescription": "Counts demand data reads that miss the LLC and the data forwarded from remote cache",
256 "Counter": "0,1,2,3",
257 "EventCode": "0xB7, 0xBB",
258 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
259 "MSRIndex": "0x1a6,0x1a7",
260 "MSRValue": "0x87f820001",
261 "SampleAfterValue": "100003",
262 "UMask": "0x1"
263 },
264 {
265 "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram",
266 "Counter": "0,1,2,3",
267 "EventCode": "0xB7, 0xBB",
268 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",
269 "MSRIndex": "0x1a6,0x1a7",
270 "MSRValue": "0x3fffc20040",
271 "SampleAfterValue": "100003",
272 "UMask": "0x1"
273 },
274 {
275 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram",
276 "Counter": "0,1,2,3",
277 "EventCode": "0xB7, 0xBB",
278 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM",
279 "MSRIndex": "0x1a6,0x1a7",
280 "MSRValue": "0x67fc00010",
281 "SampleAfterValue": "100003",
282 "UMask": "0x1"
283 },
284 {
285 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC",
286 "Counter": "0,1,2,3",
287 "EventCode": "0xB7, 0xBB",
288 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",
289 "MSRIndex": "0x1a6,0x1a7",
290 "MSRValue": "0x3fffc20010",
291 "SampleAfterValue": "100003",
292 "UMask": "0x1"
293 },
294 {
295 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram",
296 "Counter": "0,1,2,3",
297 "EventCode": "0xB7, 0xBB",
298 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM",
299 "MSRIndex": "0x1a6,0x1a7",
300 "MSRValue": "0x600400010",
301 "SampleAfterValue": "100003",
302 "UMask": "0x1"
303 },
304 {
305 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram",
306 "Counter": "0,1,2,3",
307 "EventCode": "0xB7, 0xBB",
308 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM",
309 "MSRIndex": "0x1a6,0x1a7",
310 "MSRValue": "0x67f800010",
311 "SampleAfterValue": "100003",
312 "UMask": "0x1"
313 },
314 {
315 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
316 "Counter": "0,1,2,3",
317 "EventCode": "0xB7, 0xBB",
318 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM",
319 "MSRIndex": "0x1a6,0x1a7",
320 "MSRValue": "0x107fc00010",
321 "SampleAfterValue": "100003",
322 "UMask": "0x1"
323 },
324 {
325 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache",
326 "Counter": "0,1,2,3",
327 "EventCode": "0xB7, 0xBB",
328 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
329 "MSRIndex": "0x1a6,0x1a7",
330 "MSRValue": "0x87f820010",
331 "SampleAfterValue": "100003",
332 "UMask": "0x1"
333 },
334 {
335 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC",
336 "Counter": "0,1,2,3",
337 "EventCode": "0xB7, 0xBB",
338 "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
339 "MSRIndex": "0x1a6,0x1a7",
340 "MSRValue": "0x3fffc20200",
341 "SampleAfterValue": "100003",
342 "UMask": "0x1"
343 },
344 {
345 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
346 "Counter": "0,1,2,3",
347 "EventCode": "0xB7, 0xBB",
348 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",
349 "MSRIndex": "0x1a6,0x1a7",
350 "MSRValue": "0x3fffc20080",
351 "SampleAfterValue": "100003",
352 "UMask": "0x1"
353 }
354 ]
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