1 [
2 {
3 "BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
4 "Counter": "0,1,2,3,4,5,6,7",
5 "EventCode": "0xe6",
6 "EventName": "BACLEARS.ANY",
7 "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
8 "SampleAfterValue": "200003",
9 "UMask": "0x1",
10 "Unit": "cpu_atom"
11 },
12 {
13 "BriefDescription": "Clears due to Unknown Branches.",
14 "Counter": "0,1,2,3",
15 "EventCode": "0x60",
16 "EventName": "BACLEARS.ANY",
17 "PublicDescription": "Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
18 "SampleAfterValue": "100003",
19 "UMask": "0x1",
20 "Unit": "cpu_core"
21 },
22 {
23 "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
24 "Counter": "0,1,2,3",
25 "EventCode": "0x87",
26 "EventName": "DECODE.LCP",
27 "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
28 "SampleAfterValue": "500009",
29 "UMask": "0x1",
30 "Unit": "cpu_core"
31 },
32 {
33 "BriefDescription": "Cycles the Microcode Sequencer is busy.",
34 "Counter": "0,1,2,3",
35 "EventCode": "0x87",
36 "EventName": "DECODE.MS_BUSY",
37 "SampleAfterValue": "500009",
38 "UMask": "0x2",
39 "Unit": "cpu_core"
40 },
41 {
42 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
43 "Counter": "0,1,2,3",
44 "EventCode": "0x61",
45 "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
46 "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.",
47 "SampleAfterValue": "100003",
48 "UMask": "0x2",
49 "Unit": "cpu_core"
50 },
51 {
52 "BriefDescription": "Retired ANT branches",
53 "Counter": "0,1,2,3,4,5,6,7",
54 "EventCode": "0xc6",
55 "EventName": "FRONTEND_RETIRED.ANY_ANT",
56 "MSRIndex": "0x3F7",
57 "MSRValue": "0x9",
58 "PEBS": "1",
59 "PublicDescription": "Always Not Taken (ANT) conditional retired branches (no BTB entry and not mispredicted)",
60 "SampleAfterValue": "100007",
61 "UMask": "0x3",
62 "Unit": "cpu_core"
63 },
64 {
65 "BriefDescription": "Retired Instructions who experienced DSB miss.",
66 "Counter": "0,1,2,3,4,5,6,7",
67 "EventCode": "0xc6",
68 "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
69 "MSRIndex": "0x3F7",
70 "MSRValue": "0x1",
71 "PEBS": "1",
72 "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
73 "SampleAfterValue": "100007",
74 "UMask": "0x3",
75 "Unit": "cpu_core"
76 },
77 {
78 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
79 "Counter": "0,1,2,3,4,5,6,7",
80 "EventCode": "0xc6",
81 "EventName": "FRONTEND_RETIRED.DSB_MISS",
82 "MSRIndex": "0x3F7",
83 "MSRValue": "0x11",
84 "PEBS": "1",
85 "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.",
86 "SampleAfterValue": "100007",
87 "UMask": "0x3",
88 "Unit": "cpu_core"
89 },
90 {
91 "BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss",
92 "Counter": "0,1,2,3,4,5,6,7",
93 "EventCode": "0xc6",
94 "EventName": "FRONTEND_RETIRED.ITLB_MISS",
95 "SampleAfterValue": "1000003",
96 "UMask": "0x10",
97 "Unit": "cpu_atom"
98 },
99 {
100 "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
101 "Counter": "0,1,2,3,4,5,6,7",
102 "EventCode": "0xc6",
103 "EventName": "FRONTEND_RETIRED.ITLB_MISS",
104 "MSRIndex": "0x3F7",
105 "MSRValue": "0x14",
106 "PEBS": "1",
107 "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
108 "SampleAfterValue": "100007",
109 "UMask": "0x3",
110 "Unit": "cpu_core"
111 },
112 {
113 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
114 "Counter": "0,1,2,3,4,5,6,7",
115 "EventCode": "0xc6",
116 "EventName": "FRONTEND_RETIRED.L1I_MISS",
117 "MSRIndex": "0x3F7",
118 "MSRValue": "0x12",
119 "PEBS": "1",
120 "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
121 "SampleAfterValue": "100007",
122 "UMask": "0x3",
123 "Unit": "cpu_core"
124 },
125 {
126 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
127 "Counter": "0,1,2,3,4,5,6,7",
128 "EventCode": "0xc6",
129 "EventName": "FRONTEND_RETIRED.L2_MISS",
130 "MSRIndex": "0x3F7",
131 "MSRValue": "0x13",
132 "PEBS": "1",
133 "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
134 "SampleAfterValue": "100007",
135 "UMask": "0x3",
136 "Unit": "cpu_core"
137 },
138 {
139 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
140 "Counter": "0,1,2,3,4,5,6,7",
141 "EventCode": "0xc6",
142 "EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
143 "MSRIndex": "0x3F7",
144 "MSRValue": "0x600106",
145 "PEBS": "1",
146 "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",
147 "SampleAfterValue": "100007",
148 "UMask": "0x3",
149 "Unit": "cpu_core"
150 },
151 {
152 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
153 "Counter": "0,1,2,3,4,5,6,7",
154 "EventCode": "0xc6",
155 "EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
156 "MSRIndex": "0x3F7",
157 "MSRValue": "0x608006",
158 "PEBS": "1",
159 "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
160 "SampleAfterValue": "100007",
161 "UMask": "0x3",
162 "Unit": "cpu_core"
163 },
164 {
165 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
166 "Counter": "0,1,2,3,4,5,6,7",
167 "EventCode": "0xc6",
168 "EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
169 "MSRIndex": "0x3F7",
170 "MSRValue": "0x601006",
171 "PEBS": "1",
172 "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
173 "SampleAfterValue": "100007",
174 "UMask": "0x3",
175 "Unit": "cpu_core"
176 },
177 {
178 "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
179 "Counter": "0,1,2,3,4,5,6,7",
180 "EventCode": "0xc6",
181 "EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
182 "MSRIndex": "0x3F7",
183 "MSRValue": "0x600206",
184 "PEBS": "1",
185 "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.",
186 "SampleAfterValue": "100007",
187 "UMask": "0x3",
188 "Unit": "cpu_core"
189 },
190 {
191 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
192 "Counter": "0,1,2,3,4,5,6,7",
193 "EventCode": "0xc6",
194 "EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
195 "MSRIndex": "0x3F7",
196 "MSRValue": "0x610006",
197 "PEBS": "1",
198 "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
199 "SampleAfterValue": "100007",
200 "UMask": "0x3",
201 "Unit": "cpu_core"
202 },
203 {
204 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
205 "Counter": "0,1,2,3,4,5,6,7",
206 "EventCode": "0xc6",
207 "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
208 "MSRIndex": "0x3F7",
209 "MSRValue": "0x100206",
210 "PEBS": "1",
211 "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
212 "SampleAfterValue": "100007",
213 "UMask": "0x3",
214 "Unit": "cpu_core"
215 },
216 {
217 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
218 "Counter": "0,1,2,3,4,5,6,7",
219 "EventCode": "0xc6",
220 "EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
221 "MSRIndex": "0x3F7",
222 "MSRValue": "0x602006",
223 "PEBS": "1",
224 "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
225 "SampleAfterValue": "100007",
226 "UMask": "0x3",
227 "Unit": "cpu_core"
228 },
229 {
230 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
231 "Counter": "0,1,2,3,4,5,6,7",
232 "EventCode": "0xc6",
233 "EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
234 "MSRIndex": "0x3F7",
235 "MSRValue": "0x600406",
236 "PEBS": "1",
237 "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
238 "SampleAfterValue": "100007",
239 "UMask": "0x3",
240 "Unit": "cpu_core"
241 },
242 {
243 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
244 "Counter": "0,1,2,3,4,5,6,7",
245 "EventCode": "0xc6",
246 "EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
247 "MSRIndex": "0x3F7",
248 "MSRValue": "0x620006",
249 "PEBS": "1",
250 "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
251 "SampleAfterValue": "100007",
252 "UMask": "0x3",
253 "Unit": "cpu_core"
254 },
255 {
256 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
257 "Counter": "0,1,2,3,4,5,6,7",
258 "EventCode": "0xc6",
259 "EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
260 "MSRIndex": "0x3F7",
261 "MSRValue": "0x604006",
262 "PEBS": "1",
263 "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
264 "SampleAfterValue": "100007",
265 "UMask": "0x3",
266 "Unit": "cpu_core"
267 },
268 {
269 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
270 "Counter": "0,1,2,3,4,5,6,7",
271 "EventCode": "0xc6",
272 "EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
273 "MSRIndex": "0x3F7",
274 "MSRValue": "0x600806",
275 "PEBS": "1",
276 "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
277 "SampleAfterValue": "100007",
278 "UMask": "0x3",
279 "Unit": "cpu_core"
280 },
281 {
282 "BriefDescription": "Mispredicted Retired ANT branches",
283 "Counter": "0,1,2,3,4,5,6,7",
284 "EventCode": "0xc6",
285 "EventName": "FRONTEND_RETIRED.MISP_ANT",
286 "MSRIndex": "0x3F7",
287 "MSRValue": "0x9",
288 "PEBS": "1",
289 "PublicDescription": "ANT retired branches that got just mispredicted",
290 "SampleAfterValue": "100007",
291 "UMask": "0x2",
292 "Unit": "cpu_core"
293 },
294 {
295 "BriefDescription": "FRONTEND_RETIRED.MS_FLOWS",
296 "Counter": "0,1,2,3,4,5,6,7",
297 "EventCode": "0xc6",
298 "EventName": "FRONTEND_RETIRED.MS_FLOWS",
299 "MSRIndex": "0x3F7",
300 "MSRValue": "0x8",
301 "PEBS": "1",
302 "SampleAfterValue": "100007",
303 "UMask": "0x3",
304 "Unit": "cpu_core"
305 },
306 {
307 "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
308 "Counter": "0,1,2,3,4,5,6,7",
309 "EventCode": "0xc6",
310 "EventName": "FRONTEND_RETIRED.STLB_MISS",
311 "MSRIndex": "0x3F7",
312 "MSRValue": "0x15",
313 "PEBS": "1",
314 "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
315 "SampleAfterValue": "100007",
316 "UMask": "0x3",
317 "Unit": "cpu_core"
318 },
319 {
320 "BriefDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
321 "Counter": "0,1,2,3,4,5,6,7",
322 "EventCode": "0xc6",
323 "EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
324 "MSRIndex": "0x3F7",
325 "MSRValue": "0x17",
326 "PEBS": "1",
327 "SampleAfterValue": "100007",
328 "UMask": "0x3",
329 "Unit": "cpu_core"
330 },
331 {
332 "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.",
333 "Counter": "0,1,2,3,4,5,6,7",
334 "EventCode": "0x80",
335 "EventName": "ICACHE.ACCESSES",
336 "SampleAfterValue": "200003",
337 "UMask": "0x3",
338 "Unit": "cpu_atom"
339 },
340 {
341 "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -",
342 "Counter": "0,1,2,3,4,5,6,7",
343 "EventCode": "0x80",
344 "EventName": "ICACHE.MISSES",
345 "SampleAfterValue": "200003",
346 "UMask": "0x2",
347 "Unit": "cpu_atom"
348 },
349 {
350 "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
351 "Counter": "0,1,2,3",
352 "EventCode": "0x80",
353 "EventName": "ICACHE_DATA.STALLS",
354 "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at a 32 Byte granularity.",
355 "SampleAfterValue": "500009",
356 "UMask": "0x4",
357 "Unit": "cpu_core"
358 },
359 {
360 "BriefDescription": "ICACHE_DATA.STALL_PERIODS",
361 "Counter": "0,1,2,3",
362 "CounterMask": "1",
363 "EdgeDetect": "1",
364 "EventCode": "0x80",
365 "EventName": "ICACHE_DATA.STALL_PERIODS",
366 "SampleAfterValue": "500009",
367 "UMask": "0x4",
368 "Unit": "cpu_core"
369 },
370 {
371 "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
372 "Counter": "0,1,2,3",
373 "EventCode": "0x83",
374 "EventName": "ICACHE_TAG.STALLS",
375 "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
376 "SampleAfterValue": "200003",
377 "UMask": "0x4",
378 "Unit": "cpu_core"
379 },
380 {
381 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
382 "Counter": "0,1,2,3",
383 "CounterMask": "1",
384 "EventCode": "0x79",
385 "EventName": "IDQ.DSB_CYCLES_ANY",
386 "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
387 "SampleAfterValue": "2000003",
388 "UMask": "0x8",
389 "Unit": "cpu_core"
390 },
391 {
392 "BriefDescription": "Cycles DSB is delivering optimal number of Uops",
393 "Counter": "0,1,2,3",
394 "CounterMask": "6",
395 "EventCode": "0x79",
396 "EventName": "IDQ.DSB_CYCLES_OK",
397 "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the IDQ.",
398 "SampleAfterValue": "2000003",
399 "UMask": "0x8",
400 "Unit": "cpu_core"
401 },
402 {
403 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
404 "Counter": "0,1,2,3",
405 "EventCode": "0x79",
406 "EventName": "IDQ.DSB_UOPS",
407 "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
408 "SampleAfterValue": "2000003",
409 "UMask": "0x8",
410 "Unit": "cpu_core"
411 },
412 {
413 "BriefDescription": "Cycles MITE is delivering any Uop",
414 "Counter": "0,1,2,3",
415 "CounterMask": "1",
416 "EventCode": "0x79",
417 "EventName": "IDQ.MITE_CYCLES_ANY",
418 "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
419 "SampleAfterValue": "2000003",
420 "UMask": "0x4",
421 "Unit": "cpu_core"
422 },
423 {
424 "BriefDescription": "Cycles MITE is delivering optimal number of Uops",
425 "Counter": "0,1,2,3",
426 "CounterMask": "6",
427 "EventCode": "0x79",
428 "EventName": "IDQ.MITE_CYCLES_OK",
429 "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
430 "SampleAfterValue": "2000003",
431 "UMask": "0x4",
432 "Unit": "cpu_core"
433 },
434 {
435 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
436 "Counter": "0,1,2,3",
437 "EventCode": "0x79",
438 "EventName": "IDQ.MITE_UOPS",
439 "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
440 "SampleAfterValue": "2000003",
441 "UMask": "0x4",
442 "Unit": "cpu_core"
443 },
444 {
445 "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy",
446 "Counter": "0,1,2,3",
447 "CounterMask": "1",
448 "EventCode": "0x79",
449 "EventName": "IDQ.MS_CYCLES_ANY",
450 "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
451 "SampleAfterValue": "2000003",
452 "UMask": "0x20",
453 "Unit": "cpu_core"
454 },
455 {
456 "BriefDescription": "Number of switches from DSB or MITE to the MS",
457 "Counter": "0,1,2,3",
458 "CounterMask": "1",
459 "EdgeDetect": "1",
460 "EventCode": "0x79",
461 "EventName": "IDQ.MS_SWITCHES",
462 "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
463 "SampleAfterValue": "100003",
464 "UMask": "0x20",
465 "Unit": "cpu_core"
466 },
467 {
468 "BriefDescription": "Uops initiated by MITE or Decode Stream Buffer (DSB) and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
469 "Counter": "0,1,2,3",
470 "EventCode": "0x79",
471 "EventName": "IDQ.MS_UOPS",
472 "PublicDescription": "Counts the number of uops initiated by MITE or Decode Stream Buffer (DSB) and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.",
473 "SampleAfterValue": "1000003",
474 "UMask": "0x20",
475 "Unit": "cpu_core"
476 },
477 {
478 "BriefDescription": "This event counts a subset of the Topdown Slots event that when no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.",
479 "Counter": "0,1,2,3,4,5,6,7",
480 "EventCode": "0x9c",
481 "EventName": "IDQ_BUBBLES.CORE",
482 "PublicDescription": "This event counts a subset of the Topdown Slots event that when no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations. The count may be distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.",
483 "SampleAfterValue": "1000003",
484 "UMask": "0x1",
485 "Unit": "cpu_core"
486 },
487 {
488 "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]",
489 "Counter": "0,1,2,3,4,5,6,7",
490 "CounterMask": "6",
491 "EventCode": "0x9c",
492 "EventName": "IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE",
493 "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]",
494 "SampleAfterValue": "1000003",
495 "UMask": "0x1",
496 "Unit": "cpu_core"
497 },
498 {
499 "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]",
500 "Counter": "0,1,2,3,4,5,6,7",
501 "CounterMask": "1",
502 "EventCode": "0x9c",
503 "EventName": "IDQ_BUBBLES.CYCLES_FE_WAS_OK",
504 "Invert": "1",
505 "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]",
506 "SampleAfterValue": "1000003",
507 "UMask": "0x1",
508 "Unit": "cpu_core"
509 },
510 {
511 "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",
512 "Counter": "0,1,2,3,4,5,6,7",
513 "EventCode": "0x9c",
514 "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
515 "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
516 "SampleAfterValue": "1000003",
517 "UMask": "0x1",
518 "Unit": "cpu_core"
519 },
520 {
521 "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE]",
522 "Counter": "0,1,2,3,4,5,6,7",
523 "CounterMask": "6",
524 "EventCode": "0x9c",
525 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
526 "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE]",
527 "SampleAfterValue": "1000003",
528 "UMask": "0x1",
529 "Unit": "cpu_core"
530 },
531 {
532 "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK]",
533 "Counter": "0,1,2,3,4,5,6,7",
534 "CounterMask": "1",
535 "EventCode": "0x9c",
536 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
537 "Invert": "1",
538 "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK]",
539 "SampleAfterValue": "1000003",
540 "UMask": "0x1",
541 "Unit": "cpu_core"
542 }
543 ]
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