1 [
2 {
3 "BriefDescription": "Cycles the divider is busy",
4 "Counter": "0,1,2,3",
5 "EventCode": "0x14",
6 "EventName": "ARITH.CYCLES_DIV_BUSY",
7 "SampleAfterValue": "2000000",
8 "UMask": "0x1"
9 },
10 {
11 "BriefDescription": "Divide Operations executed",
12 "Counter": "0,1,2,3",
13 "CounterMask": "1",
14 "EdgeDetect": "1",
15 "EventCode": "0x14",
16 "EventName": "ARITH.DIV",
17 "Invert": "1",
18 "SampleAfterValue": "2000000",
19 "UMask": "0x1"
20 },
21 {
22 "BriefDescription": "Multiply operations executed",
23 "Counter": "0,1,2,3",
24 "EventCode": "0x14",
25 "EventName": "ARITH.MUL",
26 "SampleAfterValue": "2000000",
27 "UMask": "0x2"
28 },
29 {
30 "BriefDescription": "BACLEAR asserted with bad target address",
31 "Counter": "0,1,2,3",
32 "EventCode": "0xE6",
33 "EventName": "BACLEAR.BAD_TARGET",
34 "SampleAfterValue": "2000000",
35 "UMask": "0x2"
36 },
37 {
38 "BriefDescription": "BACLEAR asserted, regardless of cause",
39 "Counter": "0,1,2,3",
40 "EventCode": "0xE6",
41 "EventName": "BACLEAR.CLEAR",
42 "SampleAfterValue": "2000000",
43 "UMask": "0x1"
44 },
45 {
46 "BriefDescription": "Instruction queue forced BACLEAR",
47 "Counter": "0,1,2,3",
48 "EventCode": "0xA7",
49 "EventName": "BACLEAR_FORCE_IQ",
50 "SampleAfterValue": "2000000",
51 "UMask": "0x1"
52 },
53 {
54 "BriefDescription": "Early Branch Prediciton Unit clears",
55 "Counter": "0,1,2,3",
56 "EventCode": "0xE8",
57 "EventName": "BPU_CLEARS.EARLY",
58 "SampleAfterValue": "2000000",
59 "UMask": "0x1"
60 },
61 {
62 "BriefDescription": "Late Branch Prediction Unit clears",
63 "Counter": "0,1,2,3",
64 "EventCode": "0xE8",
65 "EventName": "BPU_CLEARS.LATE",
66 "SampleAfterValue": "2000000",
67 "UMask": "0x2"
68 },
69 {
70 "BriefDescription": "Branch prediction unit missed call or return",
71 "Counter": "0,1,2,3",
72 "EventCode": "0xE5",
73 "EventName": "BPU_MISSED_CALL_RET",
74 "SampleAfterValue": "2000000",
75 "UMask": "0x1"
76 },
77 {
78 "BriefDescription": "Branch instructions decoded",
79 "Counter": "0,1,2,3",
80 "EventCode": "0xE0",
81 "EventName": "BR_INST_DECODED",
82 "SampleAfterValue": "2000000",
83 "UMask": "0x1"
84 },
85 {
86 "BriefDescription": "Branch instructions executed",
87 "Counter": "0,1,2,3",
88 "EventCode": "0x88",
89 "EventName": "BR_INST_EXEC.ANY",
90 "SampleAfterValue": "200000",
91 "UMask": "0x7f"
92 },
93 {
94 "BriefDescription": "Conditional branch instructions executed",
95 "Counter": "0,1,2,3",
96 "EventCode": "0x88",
97 "EventName": "BR_INST_EXEC.COND",
98 "SampleAfterValue": "200000",
99 "UMask": "0x1"
100 },
101 {
102 "BriefDescription": "Unconditional branches executed",
103 "Counter": "0,1,2,3",
104 "EventCode": "0x88",
105 "EventName": "BR_INST_EXEC.DIRECT",
106 "SampleAfterValue": "200000",
107 "UMask": "0x2"
108 },
109 {
110 "BriefDescription": "Unconditional call branches executed",
111 "Counter": "0,1,2,3",
112 "EventCode": "0x88",
113 "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
114 "SampleAfterValue": "20000",
115 "UMask": "0x10"
116 },
117 {
118 "BriefDescription": "Indirect call branches executed",
119 "Counter": "0,1,2,3",
120 "EventCode": "0x88",
121 "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
122 "SampleAfterValue": "20000",
123 "UMask": "0x20"
124 },
125 {
126 "BriefDescription": "Indirect non call branches executed",
127 "Counter": "0,1,2,3",
128 "EventCode": "0x88",
129 "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
130 "SampleAfterValue": "20000",
131 "UMask": "0x4"
132 },
133 {
134 "BriefDescription": "Call branches executed",
135 "Counter": "0,1,2,3",
136 "EventCode": "0x88",
137 "EventName": "BR_INST_EXEC.NEAR_CALLS",
138 "SampleAfterValue": "20000",
139 "UMask": "0x30"
140 },
141 {
142 "BriefDescription": "All non call branches executed",
143 "Counter": "0,1,2,3",
144 "EventCode": "0x88",
145 "EventName": "BR_INST_EXEC.NON_CALLS",
146 "SampleAfterValue": "200000",
147 "UMask": "0x7"
148 },
149 {
150 "BriefDescription": "Indirect return branches executed",
151 "Counter": "0,1,2,3",
152 "EventCode": "0x88",
153 "EventName": "BR_INST_EXEC.RETURN_NEAR",
154 "SampleAfterValue": "20000",
155 "UMask": "0x8"
156 },
157 {
158 "BriefDescription": "Taken branches executed",
159 "Counter": "0,1,2,3",
160 "EventCode": "0x88",
161 "EventName": "BR_INST_EXEC.TAKEN",
162 "SampleAfterValue": "200000",
163 "UMask": "0x40"
164 },
165 {
166 "BriefDescription": "Retired branch instructions (Precise Event)",
167 "Counter": "0,1,2,3",
168 "EventCode": "0xC4",
169 "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
170 "PEBS": "1",
171 "SampleAfterValue": "200000",
172 "UMask": "0x4"
173 },
174 {
175 "BriefDescription": "Retired conditional branch instructions (Precise Event)",
176 "Counter": "0,1,2,3",
177 "EventCode": "0xC4",
178 "EventName": "BR_INST_RETIRED.CONDITIONAL",
179 "PEBS": "1",
180 "SampleAfterValue": "200000",
181 "UMask": "0x1"
182 },
183 {
184 "BriefDescription": "Retired near call instructions (Precise Event)",
185 "Counter": "0,1,2,3",
186 "EventCode": "0xC4",
187 "EventName": "BR_INST_RETIRED.NEAR_CALL",
188 "PEBS": "1",
189 "SampleAfterValue": "20000",
190 "UMask": "0x2"
191 },
192 {
193 "BriefDescription": "Mispredicted branches executed",
194 "Counter": "0,1,2,3",
195 "EventCode": "0x89",
196 "EventName": "BR_MISP_EXEC.ANY",
197 "SampleAfterValue": "20000",
198 "UMask": "0x7f"
199 },
200 {
201 "BriefDescription": "Mispredicted conditional branches executed",
202 "Counter": "0,1,2,3",
203 "EventCode": "0x89",
204 "EventName": "BR_MISP_EXEC.COND",
205 "SampleAfterValue": "20000",
206 "UMask": "0x1"
207 },
208 {
209 "BriefDescription": "Mispredicted unconditional branches executed",
210 "Counter": "0,1,2,3",
211 "EventCode": "0x89",
212 "EventName": "BR_MISP_EXEC.DIRECT",
213 "SampleAfterValue": "20000",
214 "UMask": "0x2"
215 },
216 {
217 "BriefDescription": "Mispredicted non call branches executed",
218 "Counter": "0,1,2,3",
219 "EventCode": "0x89",
220 "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
221 "SampleAfterValue": "2000",
222 "UMask": "0x10"
223 },
224 {
225 "BriefDescription": "Mispredicted indirect call branches executed",
226 "Counter": "0,1,2,3",
227 "EventCode": "0x89",
228 "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
229 "SampleAfterValue": "2000",
230 "UMask": "0x20"
231 },
232 {
233 "BriefDescription": "Mispredicted indirect non call branches executed",
234 "Counter": "0,1,2,3",
235 "EventCode": "0x89",
236 "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
237 "SampleAfterValue": "2000",
238 "UMask": "0x4"
239 },
240 {
241 "BriefDescription": "Mispredicted call branches executed",
242 "Counter": "0,1,2,3",
243 "EventCode": "0x89",
244 "EventName": "BR_MISP_EXEC.NEAR_CALLS",
245 "SampleAfterValue": "2000",
246 "UMask": "0x30"
247 },
248 {
249 "BriefDescription": "Mispredicted non call branches executed",
250 "Counter": "0,1,2,3",
251 "EventCode": "0x89",
252 "EventName": "BR_MISP_EXEC.NON_CALLS",
253 "SampleAfterValue": "20000",
254 "UMask": "0x7"
255 },
256 {
257 "BriefDescription": "Mispredicted return branches executed",
258 "Counter": "0,1,2,3",
259 "EventCode": "0x89",
260 "EventName": "BR_MISP_EXEC.RETURN_NEAR",
261 "SampleAfterValue": "2000",
262 "UMask": "0x8"
263 },
264 {
265 "BriefDescription": "Mispredicted taken branches executed",
266 "Counter": "0,1,2,3",
267 "EventCode": "0x89",
268 "EventName": "BR_MISP_EXEC.TAKEN",
269 "SampleAfterValue": "20000",
270 "UMask": "0x40"
271 },
272 {
273 "BriefDescription": "Mispredicted near retired calls (Precise Event)",
274 "Counter": "0,1,2,3",
275 "EventCode": "0xC5",
276 "EventName": "BR_MISP_RETIRED.NEAR_CALL",
277 "PEBS": "1",
278 "SampleAfterValue": "2000",
279 "UMask": "0x2"
280 },
281 {
282 "BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
283 "Counter": "Fixed counter 3",
284 "EventName": "CPU_CLK_UNHALTED.REF",
285 "SampleAfterValue": "2000000"
286 },
287 {
288 "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
289 "Counter": "0,1,2,3",
290 "EventCode": "0x3C",
291 "EventName": "CPU_CLK_UNHALTED.REF_P",
292 "SampleAfterValue": "100000",
293 "UMask": "0x1"
294 },
295 {
296 "BriefDescription": "Cycles when thread is not halted (fixed counter)",
297 "Counter": "Fixed counter 2",
298 "EventName": "CPU_CLK_UNHALTED.THREAD",
299 "SampleAfterValue": "2000000"
300 },
301 {
302 "BriefDescription": "Cycles when thread is not halted (programmable counter)",
303 "Counter": "0,1,2,3",
304 "EventCode": "0x3C",
305 "EventName": "CPU_CLK_UNHALTED.THREAD_P",
306 "SampleAfterValue": "2000000"
307 },
308 {
309 "BriefDescription": "Total CPU cycles",
310 "Counter": "0,1,2,3",
311 "CounterMask": "2",
312 "EventCode": "0x3C",
313 "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
314 "Invert": "1",
315 "SampleAfterValue": "2000000"
316 },
317 {
318 "BriefDescription": "Any Instruction Length Decoder stall cycles",
319 "Counter": "0,1,2,3",
320 "EventCode": "0x87",
321 "EventName": "ILD_STALL.ANY",
322 "SampleAfterValue": "2000000",
323 "UMask": "0xf"
324 },
325 {
326 "BriefDescription": "Instruction Queue full stall cycles",
327 "Counter": "0,1,2,3",
328 "EventCode": "0x87",
329 "EventName": "ILD_STALL.IQ_FULL",
330 "SampleAfterValue": "2000000",
331 "UMask": "0x4"
332 },
333 {
334 "BriefDescription": "Length Change Prefix stall cycles",
335 "Counter": "0,1,2,3",
336 "EventCode": "0x87",
337 "EventName": "ILD_STALL.LCP",
338 "SampleAfterValue": "2000000",
339 "UMask": "0x1"
340 },
341 {
342 "BriefDescription": "Stall cycles due to BPU MRU bypass",
343 "Counter": "0,1,2,3",
344 "EventCode": "0x87",
345 "EventName": "ILD_STALL.MRU",
346 "SampleAfterValue": "2000000",
347 "UMask": "0x2"
348 },
349 {
350 "BriefDescription": "Regen stall cycles",
351 "Counter": "0,1,2,3",
352 "EventCode": "0x87",
353 "EventName": "ILD_STALL.REGEN",
354 "SampleAfterValue": "2000000",
355 "UMask": "0x8"
356 },
357 {
358 "BriefDescription": "Instructions that must be decoded by decoder 0",
359 "Counter": "0,1,2,3",
360 "EventCode": "0x18",
361 "EventName": "INST_DECODED.DEC0",
362 "SampleAfterValue": "2000000",
363 "UMask": "0x1"
364 },
365 {
366 "BriefDescription": "Instructions written to instruction queue.",
367 "Counter": "0,1,2,3",
368 "EventCode": "0x17",
369 "EventName": "INST_QUEUE_WRITES",
370 "SampleAfterValue": "2000000",
371 "UMask": "0x1"
372 },
373 {
374 "BriefDescription": "Cycles instructions are written to the instruction queue",
375 "Counter": "0,1,2,3",
376 "EventCode": "0x1E",
377 "EventName": "INST_QUEUE_WRITE_CYCLES",
378 "SampleAfterValue": "2000000",
379 "UMask": "0x1"
380 },
381 {
382 "BriefDescription": "Instructions retired (fixed counter)",
383 "Counter": "Fixed counter 1",
384 "EventName": "INST_RETIRED.ANY",
385 "SampleAfterValue": "2000000"
386 },
387 {
388 "BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
389 "Counter": "0,1,2,3",
390 "EventCode": "0xC0",
391 "EventName": "INST_RETIRED.ANY_P",
392 "PEBS": "1",
393 "SampleAfterValue": "2000000",
394 "UMask": "0x1"
395 },
396 {
397 "BriefDescription": "Retired MMX instructions (Precise Event)",
398 "Counter": "0,1,2,3",
399 "EventCode": "0xC0",
400 "EventName": "INST_RETIRED.MMX",
401 "PEBS": "1",
402 "SampleAfterValue": "2000000",
403 "UMask": "0x4"
404 },
405 {
406 "BriefDescription": "Total cycles (Precise Event)",
407 "Counter": "0,1,2,3",
408 "CounterMask": "16",
409 "EventCode": "0xC0",
410 "EventName": "INST_RETIRED.TOTAL_CYCLES",
411 "Invert": "1",
412 "PEBS": "1",
413 "SampleAfterValue": "2000000",
414 "UMask": "0x1"
415 },
416 {
417 "BriefDescription": "Total cycles (Precise Event)",
418 "Counter": "0,1,2,3",
419 "CounterMask": "16",
420 "EventCode": "0xC0",
421 "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
422 "Invert": "1",
423 "PEBS": "2",
424 "SampleAfterValue": "2000000",
425 "UMask": "0x1"
426 },
427 {
428 "BriefDescription": "Retired floating-point operations (Precise Event)",
429 "Counter": "0,1,2,3",
430 "EventCode": "0xC0",
431 "EventName": "INST_RETIRED.X87",
432 "PEBS": "1",
433 "SampleAfterValue": "2000000",
434 "UMask": "0x2"
435 },
436 {
437 "BriefDescription": "Load operations conflicting with software prefetches",
438 "Counter": "0,1",
439 "EventCode": "0x4C",
440 "EventName": "LOAD_HIT_PRE",
441 "SampleAfterValue": "200000",
442 "UMask": "0x1"
443 },
444 {
445 "BriefDescription": "Cycles when uops were delivered by the LSD",
446 "Counter": "0,1,2,3",
447 "CounterMask": "1",
448 "EventCode": "0xA8",
449 "EventName": "LSD.ACTIVE",
450 "SampleAfterValue": "2000000",
451 "UMask": "0x1"
452 },
453 {
454 "BriefDescription": "Cycles no uops were delivered by the LSD",
455 "Counter": "0,1,2,3",
456 "CounterMask": "1",
457 "EventCode": "0xA8",
458 "EventName": "LSD.INACTIVE",
459 "Invert": "1",
460 "SampleAfterValue": "2000000",
461 "UMask": "0x1"
462 },
463 {
464 "BriefDescription": "Loops that can't stream from the instruction queue",
465 "Counter": "0,1,2,3",
466 "EventCode": "0x20",
467 "EventName": "LSD_OVERFLOW",
468 "SampleAfterValue": "2000000",
469 "UMask": "0x1"
470 },
471 {
472 "BriefDescription": "Cycles machine clear asserted",
473 "Counter": "0,1,2,3",
474 "EventCode": "0xC3",
475 "EventName": "MACHINE_CLEARS.CYCLES",
476 "SampleAfterValue": "20000",
477 "UMask": "0x1"
478 },
479 {
480 "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
481 "Counter": "0,1,2,3",
482 "EventCode": "0xC3",
483 "EventName": "MACHINE_CLEARS.MEM_ORDER",
484 "SampleAfterValue": "20000",
485 "UMask": "0x2"
486 },
487 {
488 "BriefDescription": "Self-Modifying Code detected",
489 "Counter": "0,1,2,3",
490 "EventCode": "0xC3",
491 "EventName": "MACHINE_CLEARS.SMC",
492 "SampleAfterValue": "20000",
493 "UMask": "0x4"
494 },
495 {
496 "BriefDescription": "All RAT stall cycles",
497 "Counter": "0,1,2,3",
498 "EventCode": "0xD2",
499 "EventName": "RAT_STALLS.ANY",
500 "SampleAfterValue": "2000000",
501 "UMask": "0xf"
502 },
503 {
504 "BriefDescription": "Flag stall cycles",
505 "Counter": "0,1,2,3",
506 "EventCode": "0xD2",
507 "EventName": "RAT_STALLS.FLAGS",
508 "SampleAfterValue": "2000000",
509 "UMask": "0x1"
510 },
511 {
512 "BriefDescription": "Partial register stall cycles",
513 "Counter": "0,1,2,3",
514 "EventCode": "0xD2",
515 "EventName": "RAT_STALLS.REGISTERS",
516 "SampleAfterValue": "2000000",
517 "UMask": "0x2"
518 },
519 {
520 "BriefDescription": "ROB read port stalls cycles",
521 "Counter": "0,1,2,3",
522 "EventCode": "0xD2",
523 "EventName": "RAT_STALLS.ROB_READ_PORT",
524 "SampleAfterValue": "2000000",
525 "UMask": "0x4"
526 },
527 {
528 "BriefDescription": "Scoreboard stall cycles",
529 "Counter": "0,1,2,3",
530 "EventCode": "0xD2",
531 "EventName": "RAT_STALLS.SCOREBOARD",
532 "SampleAfterValue": "2000000",
533 "UMask": "0x8"
534 },
535 {
536 "BriefDescription": "Resource related stall cycles",
537 "Counter": "0,1,2,3",
538 "EventCode": "0xA2",
539 "EventName": "RESOURCE_STALLS.ANY",
540 "SampleAfterValue": "2000000",
541 "UMask": "0x1"
542 },
543 {
544 "BriefDescription": "FPU control word write stall cycles",
545 "Counter": "0,1,2,3",
546 "EventCode": "0xA2",
547 "EventName": "RESOURCE_STALLS.FPCW",
548 "SampleAfterValue": "2000000",
549 "UMask": "0x20"
550 },
551 {
552 "BriefDescription": "Load buffer stall cycles",
553 "Counter": "0,1,2,3",
554 "EventCode": "0xA2",
555 "EventName": "RESOURCE_STALLS.LOAD",
556 "SampleAfterValue": "2000000",
557 "UMask": "0x2"
558 },
559 {
560 "BriefDescription": "MXCSR rename stall cycles",
561 "Counter": "0,1,2,3",
562 "EventCode": "0xA2",
563 "EventName": "RESOURCE_STALLS.MXCSR",
564 "SampleAfterValue": "2000000",
565 "UMask": "0x40"
566 },
567 {
568 "BriefDescription": "Other Resource related stall cycles",
569 "Counter": "0,1,2,3",
570 "EventCode": "0xA2",
571 "EventName": "RESOURCE_STALLS.OTHER",
572 "SampleAfterValue": "2000000",
573 "UMask": "0x80"
574 },
575 {
576 "BriefDescription": "ROB full stall cycles",
577 "Counter": "0,1,2,3",
578 "EventCode": "0xA2",
579 "EventName": "RESOURCE_STALLS.ROB_FULL",
580 "SampleAfterValue": "2000000",
581 "UMask": "0x10"
582 },
583 {
584 "BriefDescription": "Reservation Station full stall cycles",
585 "Counter": "0,1,2,3",
586 "EventCode": "0xA2",
587 "EventName": "RESOURCE_STALLS.RS_FULL",
588 "SampleAfterValue": "2000000",
589 "UMask": "0x4"
590 },
591 {
592 "BriefDescription": "Store buffer stall cycles",
593 "Counter": "0,1,2,3",
594 "EventCode": "0xA2",
595 "EventName": "RESOURCE_STALLS.STORE",
596 "SampleAfterValue": "2000000",
597 "UMask": "0x8"
598 },
599 {
600 "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
601 "Counter": "0,1,2,3",
602 "EventCode": "0xC7",
603 "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
604 "PEBS": "1",
605 "SampleAfterValue": "200000",
606 "UMask": "0x4"
607 },
608 {
609 "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
610 "Counter": "0,1,2,3",
611 "EventCode": "0xC7",
612 "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
613 "PEBS": "1",
614 "SampleAfterValue": "200000",
615 "UMask": "0x1"
616 },
617 {
618 "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
619 "Counter": "0,1,2,3",
620 "EventCode": "0xC7",
621 "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
622 "PEBS": "1",
623 "SampleAfterValue": "200000",
624 "UMask": "0x8"
625 },
626 {
627 "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
628 "Counter": "0,1,2,3",
629 "EventCode": "0xC7",
630 "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
631 "PEBS": "1",
632 "SampleAfterValue": "200000",
633 "UMask": "0x2"
634 },
635 {
636 "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
637 "Counter": "0,1,2,3",
638 "EventCode": "0xC7",
639 "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
640 "PEBS": "1",
641 "SampleAfterValue": "200000",
642 "UMask": "0x10"
643 },
644 {
645 "BriefDescription": "Stack pointer instructions decoded",
646 "Counter": "0,1,2,3",
647 "EventCode": "0xD1",
648 "EventName": "UOPS_DECODED.ESP_FOLDING",
649 "SampleAfterValue": "2000000",
650 "UMask": "0x4"
651 },
652 {
653 "BriefDescription": "Stack pointer sync operations",
654 "Counter": "0,1,2,3",
655 "EventCode": "0xD1",
656 "EventName": "UOPS_DECODED.ESP_SYNC",
657 "SampleAfterValue": "2000000",
658 "UMask": "0x8"
659 },
660 {
661 "BriefDescription": "Uops decoded by Microcode Sequencer",
662 "Counter": "0,1,2,3",
663 "CounterMask": "1",
664 "EventCode": "0xD1",
665 "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
666 "SampleAfterValue": "2000000",
667 "UMask": "0x2"
668 },
669 {
670 "BriefDescription": "Cycles no Uops are decoded",
671 "Counter": "0,1,2,3",
672 "CounterMask": "1",
673 "EventCode": "0xD1",
674 "EventName": "UOPS_DECODED.STALL_CYCLES",
675 "Invert": "1",
676 "SampleAfterValue": "2000000",
677 "UMask": "0x1"
678 },
679 {
680 "AnyThread": "1",
681 "BriefDescription": "Cycles Uops executed on any port (core count)",
682 "Counter": "0,1,2,3",
683 "CounterMask": "1",
684 "EventCode": "0xB1",
685 "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
686 "SampleAfterValue": "2000000",
687 "UMask": "0x3f"
688 },
689 {
690 "AnyThread": "1",
691 "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
692 "Counter": "0,1,2,3",
693 "CounterMask": "1",
694 "EventCode": "0xB1",
695 "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
696 "SampleAfterValue": "2000000",
697 "UMask": "0x1f"
698 },
699 {
700 "AnyThread": "1",
701 "BriefDescription": "Uops executed on any port (core count)",
702 "Counter": "0,1,2,3",
703 "CounterMask": "1",
704 "EdgeDetect": "1",
705 "EventCode": "0xB1",
706 "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT",
707 "Invert": "1",
708 "SampleAfterValue": "2000000",
709 "UMask": "0x3f"
710 },
711 {
712 "AnyThread": "1",
713 "BriefDescription": "Uops executed on ports 0-4 (core count)",
714 "Counter": "0,1,2,3",
715 "CounterMask": "1",
716 "EdgeDetect": "1",
717 "EventCode": "0xB1",
718 "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",
719 "Invert": "1",
720 "SampleAfterValue": "2000000",
721 "UMask": "0x1f"
722 },
723 {
724 "AnyThread": "1",
725 "BriefDescription": "Cycles no Uops issued on any port (core count)",
726 "Counter": "0,1,2,3",
727 "CounterMask": "1",
728 "EventCode": "0xB1",
729 "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
730 "Invert": "1",
731 "SampleAfterValue": "2000000",
732 "UMask": "0x3f"
733 },
734 {
735 "AnyThread": "1",
736 "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
737 "Counter": "0,1,2,3",
738 "CounterMask": "1",
739 "EventCode": "0xB1",
740 "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
741 "Invert": "1",
742 "SampleAfterValue": "2000000",
743 "UMask": "0x1f"
744 },
745 {
746 "BriefDescription": "Uops executed on port 0",
747 "Counter": "0,1,2,3",
748 "EventCode": "0xB1",
749 "EventName": "UOPS_EXECUTED.PORT0",
750 "SampleAfterValue": "2000000",
751 "UMask": "0x1"
752 },
753 {
754 "BriefDescription": "Uops issued on ports 0, 1 or 5",
755 "Counter": "0,1,2,3",
756 "EventCode": "0xB1",
757 "EventName": "UOPS_EXECUTED.PORT015",
758 "SampleAfterValue": "2000000",
759 "UMask": "0x40"
760 },
761 {
762 "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
763 "Counter": "0,1,2,3",
764 "CounterMask": "1",
765 "EventCode": "0xB1",
766 "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
767 "Invert": "1",
768 "SampleAfterValue": "2000000",
769 "UMask": "0x40"
770 },
771 {
772 "BriefDescription": "Uops executed on port 1",
773 "Counter": "0,1,2,3",
774 "EventCode": "0xB1",
775 "EventName": "UOPS_EXECUTED.PORT1",
776 "SampleAfterValue": "2000000",
777 "UMask": "0x2"
778 },
779 {
780 "AnyThread": "1",
781 "BriefDescription": "Uops issued on ports 2, 3 or 4",
782 "Counter": "0,1,2,3",
783 "EventCode": "0xB1",
784 "EventName": "UOPS_EXECUTED.PORT234_CORE",
785 "SampleAfterValue": "2000000",
786 "UMask": "0x80"
787 },
788 {
789 "AnyThread": "1",
790 "BriefDescription": "Uops executed on port 2 (core count)",
791 "Counter": "0,1,2,3",
792 "EventCode": "0xB1",
793 "EventName": "UOPS_EXECUTED.PORT2_CORE",
794 "SampleAfterValue": "2000000",
795 "UMask": "0x4"
796 },
797 {
798 "AnyThread": "1",
799 "BriefDescription": "Uops executed on port 3 (core count)",
800 "Counter": "0,1,2,3",
801 "EventCode": "0xB1",
802 "EventName": "UOPS_EXECUTED.PORT3_CORE",
803 "SampleAfterValue": "2000000",
804 "UMask": "0x8"
805 },
806 {
807 "AnyThread": "1",
808 "BriefDescription": "Uops executed on port 4 (core count)",
809 "Counter": "0,1,2,3",
810 "EventCode": "0xB1",
811 "EventName": "UOPS_EXECUTED.PORT4_CORE",
812 "SampleAfterValue": "2000000",
813 "UMask": "0x10"
814 },
815 {
816 "BriefDescription": "Uops executed on port 5",
817 "Counter": "0,1,2,3",
818 "EventCode": "0xB1",
819 "EventName": "UOPS_EXECUTED.PORT5",
820 "SampleAfterValue": "2000000",
821 "UMask": "0x20"
822 },
823 {
824 "BriefDescription": "Uops issued",
825 "Counter": "0,1,2,3",
826 "EventCode": "0xE",
827 "EventName": "UOPS_ISSUED.ANY",
828 "SampleAfterValue": "2000000",
829 "UMask": "0x1"
830 },
831 {
832 "AnyThread": "1",
833 "BriefDescription": "Cycles no Uops were issued on any thread",
834 "Counter": "0,1,2,3",
835 "CounterMask": "1",
836 "EventCode": "0xE",
837 "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
838 "Invert": "1",
839 "SampleAfterValue": "2000000",
840 "UMask": "0x1"
841 },
842 {
843 "AnyThread": "1",
844 "BriefDescription": "Cycles Uops were issued on either thread",
845 "Counter": "0,1,2,3",
846 "CounterMask": "1",
847 "EventCode": "0xE",
848 "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
849 "SampleAfterValue": "2000000",
850 "UMask": "0x1"
851 },
852 {
853 "BriefDescription": "Fused Uops issued",
854 "Counter": "0,1,2,3",
855 "EventCode": "0xE",
856 "EventName": "UOPS_ISSUED.FUSED",
857 "SampleAfterValue": "2000000",
858 "UMask": "0x2"
859 },
860 {
861 "BriefDescription": "Cycles no Uops were issued",
862 "Counter": "0,1,2,3",
863 "CounterMask": "1",
864 "EventCode": "0xE",
865 "EventName": "UOPS_ISSUED.STALL_CYCLES",
866 "Invert": "1",
867 "SampleAfterValue": "2000000",
868 "UMask": "0x1"
869 },
870 {
871 "BriefDescription": "Cycles Uops are being retired",
872 "Counter": "0,1,2,3",
873 "CounterMask": "1",
874 "EventCode": "0xC2",
875 "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
876 "PEBS": "1",
877 "SampleAfterValue": "2000000",
878 "UMask": "0x1"
879 },
880 {
881 "BriefDescription": "Uops retired (Precise Event)",
882 "Counter": "0,1,2,3",
883 "EventCode": "0xC2",
884 "EventName": "UOPS_RETIRED.ANY",
885 "PEBS": "1",
886 "SampleAfterValue": "2000000",
887 "UMask": "0x1"
888 },
889 {
890 "BriefDescription": "Macro-fused Uops retired (Precise Event)",
891 "Counter": "0,1,2,3",
892 "EventCode": "0xC2",
893 "EventName": "UOPS_RETIRED.MACRO_FUSED",
894 "PEBS": "1",
895 "SampleAfterValue": "2000000",
896 "UMask": "0x4"
897 },
898 {
899 "BriefDescription": "Retirement slots used (Precise Event)",
900 "Counter": "0,1,2,3",
901 "EventCode": "0xC2",
902 "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
903 "PEBS": "1",
904 "SampleAfterValue": "2000000",
905 "UMask": "0x2"
906 },
907 {
908 "BriefDescription": "Cycles Uops are not retiring (Precise Event)",
909 "Counter": "0,1,2,3",
910 "CounterMask": "1",
911 "EventCode": "0xC2",
912 "EventName": "UOPS_RETIRED.STALL_CYCLES",
913 "Invert": "1",
914 "PEBS": "1",
915 "SampleAfterValue": "2000000",
916 "UMask": "0x1"
917 },
918 {
919 "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
920 "Counter": "0,1,2,3",
921 "CounterMask": "16",
922 "EventCode": "0xC2",
923 "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
924 "Invert": "1",
925 "PEBS": "1",
926 "SampleAfterValue": "2000000",
927 "UMask": "0x1"
928 },
929 {
930 "BriefDescription": "Uop unfusions due to FP exceptions",
931 "Counter": "0,1,2,3",
932 "EventCode": "0xDB",
933 "EventName": "UOP_UNFUSION",
934 "SampleAfterValue": "2000000",
935 "UMask": "0x1"
936 }
937 ]
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