1 [
2 {
3 "BriefDescription": "DTLB load misses",
4 "Counter": "0,1,2,3",
5 "EventCode": "0x8",
6 "EventName": "DTLB_LOAD_MISSES.ANY",
7 "SampleAfterValue": "200000",
8 "UMask": "0x1"
9 },
10 {
11 "BriefDescription": "DTLB load miss caused by low part of address",
12 "Counter": "0,1,2,3",
13 "EventCode": "0x8",
14 "EventName": "DTLB_LOAD_MISSES.PDE_MISS",
15 "SampleAfterValue": "200000",
16 "UMask": "0x20"
17 },
18 {
19 "BriefDescription": "DTLB second level hit",
20 "Counter": "0,1,2,3",
21 "EventCode": "0x8",
22 "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
23 "SampleAfterValue": "2000000",
24 "UMask": "0x10"
25 },
26 {
27 "BriefDescription": "DTLB load miss page walks complete",
28 "Counter": "0,1,2,3",
29 "EventCode": "0x8",
30 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
31 "SampleAfterValue": "200000",
32 "UMask": "0x2"
33 },
34 {
35 "BriefDescription": "DTLB misses",
36 "Counter": "0,1,2,3",
37 "EventCode": "0x49",
38 "EventName": "DTLB_MISSES.ANY",
39 "SampleAfterValue": "200000",
40 "UMask": "0x1"
41 },
42 {
43 "BriefDescription": "DTLB first level misses but second level hit",
44 "Counter": "0,1,2,3",
45 "EventCode": "0x49",
46 "EventName": "DTLB_MISSES.STLB_HIT",
47 "SampleAfterValue": "200000",
48 "UMask": "0x10"
49 },
50 {
51 "BriefDescription": "DTLB miss page walks",
52 "Counter": "0,1,2,3",
53 "EventCode": "0x49",
54 "EventName": "DTLB_MISSES.WALK_COMPLETED",
55 "SampleAfterValue": "200000",
56 "UMask": "0x2"
57 },
58 {
59 "BriefDescription": "ITLB flushes",
60 "Counter": "0,1,2,3",
61 "EventCode": "0xAE",
62 "EventName": "ITLB_FLUSH",
63 "SampleAfterValue": "2000000",
64 "UMask": "0x1"
65 },
66 {
67 "BriefDescription": "ITLB miss",
68 "Counter": "0,1,2,3",
69 "EventCode": "0x85",
70 "EventName": "ITLB_MISSES.ANY",
71 "SampleAfterValue": "200000",
72 "UMask": "0x1"
73 },
74 {
75 "BriefDescription": "ITLB miss page walks",
76 "Counter": "0,1,2,3",
77 "EventCode": "0x85",
78 "EventName": "ITLB_MISSES.WALK_COMPLETED",
79 "SampleAfterValue": "200000",
80 "UMask": "0x2"
81 },
82 {
83 "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
84 "Counter": "0,1,2,3",
85 "EventCode": "0xC8",
86 "EventName": "ITLB_MISS_RETIRED",
87 "PEBS": "1",
88 "SampleAfterValue": "200000",
89 "UMask": "0x20"
90 },
91 {
92 "BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
93 "Counter": "0,1,2,3",
94 "EventCode": "0xCB",
95 "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
96 "PEBS": "1",
97 "SampleAfterValue": "200000",
98 "UMask": "0x80"
99 },
100 {
101 "BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
102 "Counter": "0,1,2,3",
103 "EventCode": "0xC",
104 "EventName": "MEM_STORE_RETIRED.DTLB_MISS",
105 "PEBS": "1",
106 "SampleAfterValue": "200000",
107 "UMask": "0x1"
108 }
109 ]
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