1 [
2 {
3 "BriefDescription": "ES segment renames",
4 "Counter": "0,1,2,3",
5 "EventCode": "0xD5",
6 "EventName": "ES_REG_RENAMES",
7 "SampleAfterValue": "2000000",
8 "UMask": "0x1"
9 },
10 {
11 "BriefDescription": "I/O transactions",
12 "Counter": "0,1,2,3",
13 "EventCode": "0x6C",
14 "EventName": "IO_TRANSACTIONS",
15 "SampleAfterValue": "2000000",
16 "UMask": "0x1"
17 },
18 {
19 "BriefDescription": "L1I instruction fetch stall cycles",
20 "Counter": "0,1,2,3",
21 "EventCode": "0x80",
22 "EventName": "L1I.CYCLES_STALLED",
23 "SampleAfterValue": "2000000",
24 "UMask": "0x4"
25 },
26 {
27 "BriefDescription": "L1I instruction fetch hits",
28 "Counter": "0,1,2,3",
29 "EventCode": "0x80",
30 "EventName": "L1I.HITS",
31 "SampleAfterValue": "2000000",
32 "UMask": "0x1"
33 },
34 {
35 "BriefDescription": "L1I instruction fetch misses",
36 "Counter": "0,1,2,3",
37 "EventCode": "0x80",
38 "EventName": "L1I.MISSES",
39 "SampleAfterValue": "2000000",
40 "UMask": "0x2"
41 },
42 {
43 "BriefDescription": "L1I Instruction fetches",
44 "Counter": "0,1,2,3",
45 "EventCode": "0x80",
46 "EventName": "L1I.READS",
47 "SampleAfterValue": "2000000",
48 "UMask": "0x3"
49 },
50 {
51 "BriefDescription": "Large ITLB hit",
52 "Counter": "0,1,2,3",
53 "EventCode": "0x82",
54 "EventName": "LARGE_ITLB.HIT",
55 "SampleAfterValue": "200000",
56 "UMask": "0x1"
57 },
58 {
59 "BriefDescription": "Loads that partially overlap an earlier store",
60 "Counter": "0,1,2,3",
61 "EventCode": "0x3",
62 "EventName": "LOAD_BLOCK.OVERLAP_STORE",
63 "SampleAfterValue": "200000",
64 "UMask": "0x2"
65 },
66 {
67 "BriefDescription": "All loads dispatched",
68 "Counter": "0,1,2,3",
69 "EventCode": "0x13",
70 "EventName": "LOAD_DISPATCH.ANY",
71 "SampleAfterValue": "2000000",
72 "UMask": "0x7"
73 },
74 {
75 "BriefDescription": "Loads dispatched from the MOB",
76 "Counter": "0,1,2,3",
77 "EventCode": "0x13",
78 "EventName": "LOAD_DISPATCH.MOB",
79 "SampleAfterValue": "2000000",
80 "UMask": "0x4"
81 },
82 {
83 "BriefDescription": "Loads dispatched that bypass the MOB",
84 "Counter": "0,1,2,3",
85 "EventCode": "0x13",
86 "EventName": "LOAD_DISPATCH.RS",
87 "SampleAfterValue": "2000000",
88 "UMask": "0x1"
89 },
90 {
91 "BriefDescription": "Loads dispatched from stage 305",
92 "Counter": "0,1,2,3",
93 "EventCode": "0x13",
94 "EventName": "LOAD_DISPATCH.RS_DELAYED",
95 "SampleAfterValue": "2000000",
96 "UMask": "0x2"
97 },
98 {
99 "BriefDescription": "False dependencies due to partial address aliasing",
100 "Counter": "0,1,2,3",
101 "EventCode": "0x7",
102 "EventName": "PARTIAL_ADDRESS_ALIAS",
103 "SampleAfterValue": "200000",
104 "UMask": "0x1"
105 },
106 {
107 "BriefDescription": "All Store buffer stall cycles",
108 "Counter": "0,1,2,3",
109 "EventCode": "0x4",
110 "EventName": "SB_DRAIN.ANY",
111 "SampleAfterValue": "200000",
112 "UMask": "0x7"
113 },
114 {
115 "BriefDescription": "Segment rename stall cycles",
116 "Counter": "0,1,2,3",
117 "EventCode": "0xD4",
118 "EventName": "SEG_RENAME_STALLS",
119 "SampleAfterValue": "2000000",
120 "UMask": "0x1"
121 },
122 {
123 "BriefDescription": "Snoop code requests",
124 "Counter": "0,1,2,3",
125 "EventCode": "0xB4",
126 "EventName": "SNOOPQ_REQUESTS.CODE",
127 "SampleAfterValue": "100000",
128 "UMask": "0x4"
129 },
130 {
131 "BriefDescription": "Snoop data requests",
132 "Counter": "0,1,2,3",
133 "EventCode": "0xB4",
134 "EventName": "SNOOPQ_REQUESTS.DATA",
135 "SampleAfterValue": "100000",
136 "UMask": "0x1"
137 },
138 {
139 "BriefDescription": "Snoop invalidate requests",
140 "Counter": "0,1,2,3",
141 "EventCode": "0xB4",
142 "EventName": "SNOOPQ_REQUESTS.INVALIDATE",
143 "SampleAfterValue": "100000",
144 "UMask": "0x2"
145 },
146 {
147 "BriefDescription": "Outstanding snoop code requests",
148 "Counter": "0",
149 "EventCode": "0xB3",
150 "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE",
151 "SampleAfterValue": "2000000",
152 "UMask": "0x4"
153 },
154 {
155 "BriefDescription": "Cycles snoop code requests queued",
156 "Counter": "0",
157 "CounterMask": "1",
158 "EventCode": "0xB3",
159 "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY",
160 "SampleAfterValue": "2000000",
161 "UMask": "0x4"
162 },
163 {
164 "BriefDescription": "Outstanding snoop data requests",
165 "Counter": "0",
166 "EventCode": "0xB3",
167 "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA",
168 "SampleAfterValue": "2000000",
169 "UMask": "0x1"
170 },
171 {
172 "BriefDescription": "Cycles snoop data requests queued",
173 "Counter": "0",
174 "CounterMask": "1",
175 "EventCode": "0xB3",
176 "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY",
177 "SampleAfterValue": "2000000",
178 "UMask": "0x1"
179 },
180 {
181 "BriefDescription": "Outstanding snoop invalidate requests",
182 "Counter": "0",
183 "EventCode": "0xB3",
184 "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE",
185 "SampleAfterValue": "2000000",
186 "UMask": "0x2"
187 },
188 {
189 "BriefDescription": "Cycles snoop invalidate requests queued",
190 "Counter": "0",
191 "CounterMask": "1",
192 "EventCode": "0xB3",
193 "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY",
194 "SampleAfterValue": "2000000",
195 "UMask": "0x2"
196 },
197 {
198 "BriefDescription": "Thread responded HIT to snoop",
199 "Counter": "0,1,2,3",
200 "EventCode": "0xB8",
201 "EventName": "SNOOP_RESPONSE.HIT",
202 "SampleAfterValue": "100000",
203 "UMask": "0x1"
204 },
205 {
206 "BriefDescription": "Thread responded HITE to snoop",
207 "Counter": "0,1,2,3",
208 "EventCode": "0xB8",
209 "EventName": "SNOOP_RESPONSE.HITE",
210 "SampleAfterValue": "100000",
211 "UMask": "0x2"
212 },
213 {
214 "BriefDescription": "Thread responded HITM to snoop",
215 "Counter": "0,1,2,3",
216 "EventCode": "0xB8",
217 "EventName": "SNOOP_RESPONSE.HITM",
218 "SampleAfterValue": "100000",
219 "UMask": "0x4"
220 },
221 {
222 "BriefDescription": "Super Queue full stall cycles",
223 "Counter": "0,1,2,3",
224 "EventCode": "0xF6",
225 "EventName": "SQ_FULL_STALL_CYCLES",
226 "SampleAfterValue": "2000000",
227 "UMask": "0x1"
228 }
229 ]
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