1 {
2 "SkipList": [
3 "tsx_aborted_cycles",
4 "tsx_transactional_cycles",
5 "C2_Pkg_Residency",
6 "C6_Pkg_Residency",
7 "C1_Core_Residency",
8 "C6_Core_Residency",
9 "tma_false_sharing",
10 "tma_remote_cache",
11 "tma_contested_accesses"
12 ],
13 "RelationshipRules": [
14 {
15 "RuleIndex": 1,
16 "Formula": "a+b",
17 "TestType": "RelationshipTest",
18 "RangeLower": "c",
19 "RangeUpper": "c",
20 "ErrorThreshold": 5.0,
21 "Description": "Intel(R) Optane(TM) Persistent Memory(PMEM) bandwidth total includes Intel(R) Optane(TM) Persistent Memory(PMEM) read bandwidth and Intel(R) Optane(TM) Persistent Memory(PMEM) write bandwidth",
22 "Metrics": [
23 {
24 "Name": "pmem_memory_bandwidth_read",
25 "Alias": "a"
26 },
27 {
28 "Name": "pmem_memory_bandwidth_write",
29 "Alias": "b"
30 },
31 {
32 "Name": "pmem_memory_bandwidth_total",
33 "Alias": "c"
34 }
35 ]
36 },
37 {
38 "RuleIndex": 2,
39 "Formula": "a+b",
40 "TestType": "RelationshipTest",
41 "RangeLower": "c",
42 "RangeUpper": "c",
43 "ErrorThreshold": 5.0,
44 "Description": "DDR memory bandwidth total includes DDR memory read bandwidth and DDR memory write bandwidth",
45 "Metrics": [
46 {
47 "Name": "memory_bandwidth_read",
48 "Alias": "a"
49 },
50 {
51 "Name": "memory_bandwidth_write",
52 "Alias": "b"
53 },
54 {
55 "Name": "memory_bandwidth_total",
56 "Alias": "c"
57 }
58 ]
59 },
60 {
61 "RuleIndex": 3,
62 "Formula": "a+b",
63 "TestType": "RelationshipTest",
64 "RangeLower": "100",
65 "RangeUpper": "100",
66 "ErrorThreshold": 5.0,
67 "Description": "Total memory read accesses includes memory reads from last level cache (LLC) addressed to local DRAM and memory reads from the last level cache (LLC) addressed to remote DRAM.",
68 "Metrics": [
69 {
70 "Name": "numa_reads_addressed_to_local_dram",
71 "Alias": "a"
72 },
73 {
74 "Name": "numa_reads_addressed_to_remote_dram",
75 "Alias": "b"
76 }
77 ]
78 },
79 {
80 "RuleIndex": 4,
81 "Formula": "a",
82 "TestType": "SingleMetricTest",
83 "RangeLower": "0.125",
84 "RangeUpper": "",
85 "ErrorThreshold": "",
86 "Description": "",
87 "Metrics": [
88 {
89 "Name": "cpi",
90 "Alias": "a"
91 }
92 ]
93 },
94 {
95 "RuleIndex": 5,
96 "Formula": "",
97 "TestType": "SingleMetricTest",
98 "RangeLower": "0",
99 "RangeUpper": "1",
100 "ErrorThreshold": 5.0,
101 "Description": "Ratio values should be within value range [0,1)",
102 "Metrics": [
103 {
104 "Name": "loads_per_instr",
105 "Alias": ""
106 },
107 {
108 "Name": "stores_per_instr",
109 "Alias": ""
110 },
111 {
112 "Name": "l1d_mpi",
113 "Alias": ""
114 },
115 {
116 "Name": "l1d_demand_data_read_hits_per_instr",
117 "Alias": ""
118 },
119 {
120 "Name": "l1_i_code_read_misses_with_prefetches_per_instr",
121 "Alias": ""
122 },
123 {
124 "Name": "l2_demand_data_read_hits_per_instr",
125 "Alias": ""
126 },
127 {
128 "Name": "l2_mpi",
129 "Alias": ""
130 },
131 {
132 "Name": "l2_demand_data_read_mpi",
133 "Alias": ""
134 },
135 {
136 "Name": "l2_demand_code_mpi",
137 "Alias": ""
138 }
139 ]
140 },
141 {
142 "RuleIndex": 6,
143 "Formula": "a+b+c+d",
144 "TestType": "RelationshipTest",
145 "RangeLower": "100",
146 "RangeUpper": "100",
147 "ErrorThreshold": 5.0,
148 "Description": "Sum of TMA level 1 metrics should be 100%",
149 "Metrics": [
150 {
151 "Name": "tma_frontend_bound",
152 "Alias": "a"
153 },
154 {
155 "Name": "tma_bad_speculation",
156 "Alias": "b"
157 },
158 {
159 "Name": "tma_backend_bound",
160 "Alias": "c"
161 },
162 {
163 "Name": "tma_retiring",
164 "Alias": "d"
165 }
166 ]
167 },
168 {
169 "RuleIndex": 7,
170 "Formula": "a+b",
171 "TestType": "RelationshipTest",
172 "RangeLower": "c",
173 "RangeUpper": "c",
174 "ErrorThreshold": 5.0,
175 "Description": "Sum of the level 2 children should equal level 1 parent",
176 "Metrics": [
177 {
178 "Name": "tma_fetch_latency",
179 "Alias": "a"
180 },
181 {
182 "Name": "tma_fetch_bandwidth",
183 "Alias": "b"
184 },
185 {
186 "Name": "tma_frontend_bound",
187 "Alias": "c"
188 }
189 ]
190 },
191 {
192 "RuleIndex": 8,
193 "Formula": "a+b",
194 "TestType": "RelationshipTest",
195 "RangeLower": "c",
196 "RangeUpper": "c",
197 "ErrorThreshold": 5.0,
198 "Description": "Sum of the level 2 children should equal level 1 parent",
199 "Metrics": [
200 {
201 "Name": "tma_branch_mispredicts",
202 "Alias": "a"
203 },
204 {
205 "Name": "tma_machine_clears",
206 "Alias": "b"
207 },
208 {
209 "Name": "tma_bad_speculation",
210 "Alias": "c"
211 }
212 ]
213 },
214 {
215 "RuleIndex": 9,
216 "Formula": "a+b",
217 "TestType": "RelationshipTest",
218 "RangeLower": "c",
219 "RangeUpper": "c",
220 "ErrorThreshold": 5.0,
221 "Description": "Sum of the level 2 children should equal level 1 parent",
222 "Metrics": [
223 {
224 "Name": "tma_memory_bound",
225 "Alias": "a"
226 },
227 {
228 "Name": "tma_core_bound",
229 "Alias": "b"
230 },
231 {
232 "Name": "tma_backend_bound",
233 "Alias": "c"
234 }
235 ]
236 },
237 {
238 "RuleIndex": 10,
239 "Formula": "a+b",
240 "TestType": "RelationshipTest",
241 "RangeLower": "c",
242 "RangeUpper": "c",
243 "ErrorThreshold": 5.0,
244 "Description": "Sum of the level 2 children should equal level 1 parent",
245 "Metrics": [
246 {
247 "Name": "tma_light_operations",
248 "Alias": "a"
249 },
250 {
251 "Name": "tma_heavy_operations",
252 "Alias": "b"
253 },
254 {
255 "Name": "tma_retiring",
256 "Alias": "c"
257 }
258 ]
259 },
260 {
261 "RuleIndex": 11,
262 "Formula": "a+b+c",
263 "TestType": "RelationshipTest",
264 "RangeLower": "100",
265 "RangeUpper": "100",
266 "ErrorThreshold": 5.0,
267 "Description": "The all_requests includes the memory_page_empty, memory_page_misses, and memory_page_hits equals.",
268 "Metrics": [
269 {
270 "Name": "memory_page_empty_vs_all_requests",
271 "Alias": "a"
272 },
273 {
274 "Name": "memory_page_misses_vs_all_requests",
275 "Alias": "b"
276 },
277 {
278 "Name": "memory_page_hits_vs_all_requests",
279 "Alias": "c"
280 }
281 ]
282 },
283 {
284 "RuleIndex": 12,
285 "Formula": "a-b",
286 "TestType": "RelationshipTest",
287 "RangeLower": "0",
288 "RangeUpper": "",
289 "ErrorThreshold": 5.0,
290 "Description": "CPU utilization in kernel mode should always be <= cpu utilization",
291 "Metrics": [
292 {
293 "Name": "cpu_utilization",
294 "Alias": "a"
295 },
296 {
297 "Name": "cpu_utilization_in_kernel_mode",
298 "Alias": "b"
299 }
300 ]
301 },
302 {
303 "RuleIndex": 13,
304 "Formula": "a-b",
305 "TestType": "RelationshipTest",
306 "RangeLower": "0",
307 "RangeUpper": "",
308 "ErrorThreshold": 5.0,
309 "Description": "Total L2 misses per instruction should be >= L2 demand data read misses per instruction",
310 "Metrics": [
311 {
312 "Name": "l2_mpi",
313 "Alias": "a"
314 },
315 {
316 "Name": "l2_demand_data_read_mpi",
317 "Alias": "b"
318 }
319 ]
320 },
321 {
322 "RuleIndex": 14,
323 "Formula": "a-b",
324 "TestType": "RelationshipTest",
325 "RangeLower": "0",
326 "RangeUpper": "",
327 "ErrorThreshold": 5.0,
328 "Description": "Total L2 misses per instruction should be >= L2 demand code misses per instruction",
329 "Metrics": [
330 {
331 "Name": "l2_mpi",
332 "Alias": "a"
333 },
334 {
335 "Name": "l2_demand_code_mpi",
336 "Alias": "b"
337 }
338 ]
339 },
340 {
341 "RuleIndex": 15,
342 "Formula": "b+c+d",
343 "TestType": "RelationshipTest",
344 "RangeLower": "a",
345 "RangeUpper": "a",
346 "ErrorThreshold": 5.0,
347 "Description": "L3 data read, rfo, code misses per instruction equals total L3 misses per instruction.",
348 "Metrics": [
349 {
350 "Name": "llc_mpi",
351 "Alias": "a"
352 },
353 {
354 "Name": "llc_data_read_mpi_demand_plus_prefetch",
355 "Alias": "b"
356 },
357 {
358 "Name": "llc_rfo_read_mpi_demand_plus_prefetch",
359 "Alias": "c"
360 },
361 {
362 "Name": "llc_code_read_mpi_demand_plus_prefetch",
363 "Alias": "d"
364 }
365 ]
366 },
367 {
368 "RuleIndex": 16,
369 "Formula": "a",
370 "TestType": "SingleMetricTest",
371 "RangeLower": "0",
372 "RangeUpper": "8",
373 "ErrorThreshold": 0.0,
374 "Description": "Setting generous range for allowable frequencies",
375 "Metrics": [
376 {
377 "Name": "uncore_freq",
378 "Alias": "a"
379 }
380 ]
381 },
382 {
383 "RuleIndex": 17,
384 "Formula": "a",
385 "TestType": "SingleMetricTest",
386 "RangeLower": "0",
387 "RangeUpper": "8",
388 "ErrorThreshold": 0.0,
389 "Description": "Setting generous range for allowable frequencies",
390 "Metrics": [
391 {
392 "Name": "cpu_operating_frequency",
393 "Alias": "a"
394 }
395 ]
396 }
397 ]
398 }
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