1 /* SPDX-License-Identifier: LGPL-2.1 OR MIT */
2
3 /*
4 * RSEQ_SIG uses the trap4 instruction. As Linux does not make use of the
5 * access-register mode nor the linkage stack this instruction will always
6 * cause a special-operation exception (the trap-enabled bit in the DUCT
7 * is and will stay 0). The instruction pattern is
8 * b2 ff 0f ff trap4 4095(%r0)
9 */
10 #define RSEQ_SIG 0xB2FF0FFF
11
12 #define rseq_smp_mb() __asm__ __volatile__ ("bcr 15,0" ::: "memory")
13 #define rseq_smp_rmb() rseq_smp_mb()
14 #define rseq_smp_wmb() rseq_smp_mb()
15
16 #define rseq_smp_load_acquire(p) \
17 __extension__ ({ \
18 rseq_unqual_scalar_typeof(*(p)) ____p1 = RSEQ_READ_ONCE(*(p)); \
19 rseq_barrier(); \
20 ____p1; \
21 })
22
23 #define rseq_smp_acquire__after_ctrl_dep() rseq_smp_rmb()
24
25 #define rseq_smp_store_release(p, v) \
26 do { \
27 rseq_barrier(); \
28 RSEQ_WRITE_ONCE(*(p), v); \
29 } while (0)
30
31 #ifdef __s390x__
32
33 #define LONG_L "lg"
34 #define LONG_S "stg"
35 #define LONG_LT_R "ltgr"
36 #define LONG_CMP "cg"
37 #define LONG_CMP_R "cgr"
38 #define LONG_ADDI "aghi"
39 #define LONG_ADD_R "agr"
40
41 #define __RSEQ_ASM_DEFINE_TABLE(label, version, flags, \
42 start_ip, post_commit_offset, abort_ip) \
43 ".pushsection __rseq_cs, \"aw\"\n\t" \
44 ".balign 32\n\t" \
45 __rseq_str(label) ":\n\t" \
46 ".long " __rseq_str(version) ", " __rseq_str(flags) "\n\t" \
47 ".quad " __rseq_str(start_ip) ", " __rseq_str(post_commit_offset) ", " __rseq_str(abort_ip) "\n\t" \
48 ".popsection\n\t" \
49 ".pushsection __rseq_cs_ptr_array, \"aw\"\n\t" \
50 ".quad " __rseq_str(label) "b\n\t" \
51 ".popsection\n\t"
52
53 /*
54 * Exit points of a rseq critical section consist of all instructions outside
55 * of the critical section where a critical section can either branch to or
56 * reach through the normal course of its execution. The abort IP and the
57 * post-commit IP are already part of the __rseq_cs section and should not be
58 * explicitly defined as additional exit points. Knowing all exit points is
59 * useful to assist debuggers stepping over the critical section.
60 */
61 #define RSEQ_ASM_DEFINE_EXIT_POINT(start_ip, exit_ip) \
62 ".pushsection __rseq_exit_point_array, \"aw\"\n\t" \
63 ".quad " __rseq_str(start_ip) ", " __rseq_str(exit_ip) "\n\t" \
64 ".popsection\n\t"
65
66 #elif __s390__
67
68 #define __RSEQ_ASM_DEFINE_TABLE(label, version, flags, \
69 start_ip, post_commit_offset, abort_ip) \
70 ".pushsection __rseq_cs, \"aw\"\n\t" \
71 ".balign 32\n\t" \
72 __rseq_str(label) ":\n\t" \
73 ".long " __rseq_str(version) ", " __rseq_str(flags) "\n\t" \
74 ".long 0x0, " __rseq_str(start_ip) ", 0x0, " __rseq_str(post_commit_offset) ", 0x0, " __rseq_str(abort_ip) "\n\t" \
75 ".popsection\n\t" \
76 ".pushsection __rseq_cs_ptr_array, \"aw\"\n\t" \
77 ".long 0x0, " __rseq_str(label) "b\n\t" \
78 ".popsection\n\t"
79
80 /*
81 * Exit points of a rseq critical section consist of all instructions outside
82 * of the critical section where a critical section can either branch to or
83 * reach through the normal course of its execution. The abort IP and the
84 * post-commit IP are already part of the __rseq_cs section and should not be
85 * explicitly defined as additional exit points. Knowing all exit points is
86 * useful to assist debuggers stepping over the critical section.
87 */
88 #define RSEQ_ASM_DEFINE_EXIT_POINT(start_ip, exit_ip) \
89 ".pushsection __rseq_exit_point_array, \"aw\"\n\t" \
90 ".long 0x0, " __rseq_str(start_ip) ", 0x0, " __rseq_str(exit_ip) "\n\t" \
91 ".popsection\n\t"
92
93 #define LONG_L "l"
94 #define LONG_S "st"
95 #define LONG_LT_R "ltr"
96 #define LONG_CMP "c"
97 #define LONG_CMP_R "cr"
98 #define LONG_ADDI "ahi"
99 #define LONG_ADD_R "ar"
100
101 #endif
102
103 #define RSEQ_ASM_DEFINE_TABLE(label, start_ip, post_commit_ip, abort_ip) \
104 __RSEQ_ASM_DEFINE_TABLE(label, 0x0, 0x0, start_ip, \
105 (post_commit_ip - start_ip), abort_ip)
106
107 #define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs) \
108 RSEQ_INJECT_ASM(1) \
109 "larl %%r0, " __rseq_str(cs_label) "\n\t" \
110 LONG_S " %%r0, %[" __rseq_str(rseq_cs) "]\n\t" \
111 __rseq_str(label) ":\n\t"
112
113 #define RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, label) \
114 RSEQ_INJECT_ASM(2) \
115 "c %[" __rseq_str(cpu_id) "], %[" __rseq_str(current_cpu_id) "]\n\t" \
116 "jnz " __rseq_str(label) "\n\t"
117
118 #define RSEQ_ASM_DEFINE_ABORT(label, teardown, abort_label) \
119 ".pushsection __rseq_failure, \"ax\"\n\t" \
120 ".long " __rseq_str(RSEQ_SIG) "\n\t" \
121 __rseq_str(label) ":\n\t" \
122 teardown \
123 "jg %l[" __rseq_str(abort_label) "]\n\t" \
124 ".popsection\n\t"
125
126 #define RSEQ_ASM_DEFINE_CMPFAIL(label, teardown, cmpfail_label) \
127 ".pushsection __rseq_failure, \"ax\"\n\t" \
128 __rseq_str(label) ":\n\t" \
129 teardown \
130 "jg %l[" __rseq_str(cmpfail_label) "]\n\t" \
131 ".popsection\n\t"
132
133 /* Per-cpu-id indexing. */
134
135 #define RSEQ_TEMPLATE_CPU_ID
136 #define RSEQ_TEMPLATE_MO_RELAXED
137 #include "rseq-s390-bits.h"
138 #undef RSEQ_TEMPLATE_MO_RELAXED
139
140 #define RSEQ_TEMPLATE_MO_RELEASE
141 #include "rseq-s390-bits.h"
142 #undef RSEQ_TEMPLATE_MO_RELEASE
143 #undef RSEQ_TEMPLATE_CPU_ID
144
145 /* Per-mm-cid indexing. */
146
147 #define RSEQ_TEMPLATE_MM_CID
148 #define RSEQ_TEMPLATE_MO_RELAXED
149 #include "rseq-s390-bits.h"
150 #undef RSEQ_TEMPLATE_MO_RELAXED
151
152 #define RSEQ_TEMPLATE_MO_RELEASE
153 #include "rseq-s390-bits.h"
154 #undef RSEQ_TEMPLATE_MO_RELEASE
155 #undef RSEQ_TEMPLATE_MM_CID
156
157 /* APIs which are not based on cpu ids. */
158
159 #define RSEQ_TEMPLATE_CPU_ID_NONE
160 #define RSEQ_TEMPLATE_MO_RELAXED
161 #include "rseq-s390-bits.h"
162 #undef RSEQ_TEMPLATE_MO_RELAXED
163 #undef RSEQ_TEMPLATE_CPU_ID_NONE
164
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